NT512S72V4PA0GR-75B 查看數據表（PDF） - Nanya Technology
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NT512S72V4PA0GR-75B
Nanya Technology
NT512S72V4PA0GR-75B Datasheet PDF : 12 Pages
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NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
Input/Output Functional Description
Symbol
CK0 - CK3
CKE0
S0 , S2
Type
Input
Input
Input
Polarity
Positive
Edge
Active
High
Active
Low
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock. CK0 drives the PLL. CK1, CK2 andCK3 are terminated.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS , CAS , WE
Input
Active
Low
When sampled at the positive rising edge of the clock, RAS , CAS , WE define the operation to be
executed by the SDRAM.
BA0, BA1
A0 - A9
A10/AP
A11, A12
DQ0 - DQ63,
CB0 - CB7
DQMB0 -DQMB7
REGE
SA0 – SA2
SDA
SCL
WP
Input
-
Input
-
Input
-
/Output
Input
Active
High
Input
Active
High
(Register
Mode
Enable)
Input
-
Input
-
/Output
Input
-
Input
Active
High
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,A11)
when sampled at the rising clock edge. In addition to the column address, AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is
selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which
bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of
BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins .
The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high
impedance state when sampled high. In Read mode, DQMB has a latency of three clock cycles in
Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB
has a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high.
The Register Enable pin must be held high for proper registered mode operation (signals re-driven
to the SDRAMs when the clock rises, and held valid until the next rising clock).
Address inputs. Connected to either VDD or VSS on the system board to configure the Serial
Presence Detect EEPROM address.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus time to VDD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pull up.
This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD
EEPROM.
VDD , VSS
Supply
Power and ground for the module.
Preliminary 06 / 2001
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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