NT512S72V4PA0GR-75B 查看數據表（PDF） - Nanya Technology

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NT512S72V4PA0GR-75B

64Mx72 bit One Bank Registered SDRAM Module based on 64Mx4, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Nanya Technology 

NT512S72V4PA0GR

512MB : 64M x 72

Registered SDRAM Module

AC Characteristics (TA =0 to 70 °C , VDD =3.3 ± 0.3V)

1. An initial pause of 200ms, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a

minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point.

3. The Transition time is measured between VIH and VIL (or between VIL and VIH ).

4. AC measurements assume t T =1.2ns (1 Volt/ns rise time).

5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH ) in a

monotonic manner.

6. A 1ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.

7. All timings are specified at the input receiver of the signal. This allows times to be specified at the end of a transmission line versus at the

DIMM connector which may display significant reflections. Refer to the device specifications for non-skew adjusted timings.

AC Output Load Circuits

Clock

tCKL

tSETUP tHOLD

Input

Output

1.4V

tAC

tLZ

tT

tCKH

VIH

1.4V

VIL

tOH

1.4V

Output

Zo = 50 ohm

AC Output Load Circuit

50 pF

Preliminary 06 / 2001

7

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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