M36W108AB100ZM5T 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M36W108AB100ZM5T

8 Mbit (1Mb x8, Boot Block) Flash Memory and 1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product

STMicroelectronics 

M36W108AT, M36W108AB

Table 9. Flash Instructions (1)

Mne.

Instr. Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Read/Reset

RD (2,4) Memory

Array

Addr. (3,6)

1+

Data

Addr. (3,6)

3+

Data

X

F0h

555h

AAh

Read Memory Array until a new write cycle is initiated.

2AAh

55h

555h

F0h

Read Memory Array until a new write cycle

is initiated.

AS (4) Auto Select

Addr. (3,6)

3+

Data

555h

AAh

2AAh

55h

555h

90h

Read Electronic Signature until a new write

cycle is initiated. See Note 5.

PG Program

Addr. (3,6)

4

Data

555h

AAh

2AAh

55h

555h

A0h

Program

Address Read Data Polling or Toggle Bit

Program until Program completes.

Data

BE Block Erase

Addr. (3,6)

6

Data

555h

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h

Block Additional

Address Block (7)

30h

30h

CE Chip Erase

Addr. (3,6)

6

Data

555h

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h

555h

10h

Note 8

ES (9)

Erase

Suspend

Addr. (3,6)

1

Data

X

Read until Toggle stops, then read all the data needed from any

B0h Block(s) not being erased then Resume Erase.

ER

Erase

Resume

Addr. (3,6)

1

Data

X

Read Data Polling or Toggle Bits until Erase completes or Erase

30h is suspended another time.

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before

starting any new operation (see Table 15 and Figure 8).

3. X = Don’t care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device

code.

6. For Coded cycles address inputs A11-A19 are don’t care.

7. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be

verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit

until Erase is completed or suspended.

8. Read Data Polling, Toggle bits or RB until Erase completes.

9. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

10/36

Share Link: