M41T64(2004) 查看數據表（PDF） - STMicroelectronics

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M41T64
(Rev.:2004)

Serial Access Real-Time Clock with Alarms

STMicroelectronics 

M41T62/63/64/65

Acknowledge. Each byte of eight bits is followed

by one Acknowledge Bit. This Acknowledge Bit is

a low level put on the bus by the receiver whereas

the master generates an extra acknowledge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

Figure 14. Serial Bus Data Transfer Sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

Figure 15. Acknowledgement Sequence

START

SCL FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

MSB

DATA OUTPUT

BY RECEIVER

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

AI00601

8/31

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