M41T315W-85MH6E 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M41T315W-85MH6E

Serial access phantom RTC supervisor

STMicroelectronics 

Operation

2

Operation

M41T315Y, M41T315V, M41T315W

Figure 6 on page 11 illustrates the main elements of the device. The following paragraphs

describe the signals and functions.

Communication with the clock is established by pattern recognition of a serial bit stream of

64 bits which must be matched by executing 64 consecutive WRITE cycles containing the

proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern

are directed to memory via the chip enable output pin (CEO).

After recognition is established, the next 64 READ or WRITE Cycles either extract or update

data in the clock and CEO remains high during this time, disabling the connected memory

(see Table 2 on page 11).

Data transfer to and from the timekeeping function is accomplished with a serial bit stream

under control of chip enable input (CEI), output enable (OE), and WRITE enable (WE).

Initially, a READ cycle using the CEI and OE control of the clock starts the pattern

recognition sequence by moving the pointer to the first bit of the 64-bit comparison register.

Next, 64 consecutive WRITE cycles are executed using the CEI and WE control of the clock.

These 64 WRITE cycles are used only to gain access to the clock.

When the first WRITE cycle is executed, it is compared to the first bit of the 64-bit

comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next WRITE cycle.

If a match is not found, the pointer does not advance and all subsequent WRITE cycles are

ignored. If a READ cycle occurs at any time during pattern recognition, the present

sequence is aborted and the comparison register pointer is reset. Pattern recognition

continues for a total of 64 WRITE cycles as described above until all the bits in the

comparison register have been matched (see Figure 8 on page 14).

With a correct match for 64 bits, access to the registers is enabled and data transfer to or

from the timekeeping registers may proceed. The next 64 cycles will cause the device to

either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE

pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles

without interrupting the pattern recognition sequence or data transfer sequence to the

device.

For a SO16 pin package, a standard 32.768 kHz quartz crystal can be directly connected to

the M41T315Y/V/W via pins 1 and 2 (XI, XO). The crystal selected for use should have a

specified load capacitance (CL) of 12.5 pF (see Table 10 on page 21).

10/30

Share Link: