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M470L3224BT0 查看數據表(PDF) - Samsung

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M470L3224BT0
Samsung
Samsung Samsung
M470L3224BT0 Datasheet PDF : 14 Pages
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M470L3224BT0
200pin DDR SDRAM SODIMM
M470L3224BT0 200pin DDR SDRAM SODIMM
32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16
GENERAL DESCRIPTION
The Samsung M470L3224BT0 is 32M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 256Mb DDR SDRAM respectively.
The Samsung M470L3224BT0 consists of eight CMOS 16M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 200pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L3224BT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
M470L3224BT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L3224BT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M470L3224BT0-C(L)A0 100MHz(10ns@CL=2)
Interface
SSTL_2
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
•PCB : Height 1250 (mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
1 VREF
3 VSS
5 DQ0
7 DQ1
9 VDD
11 DQS0
13 DQ2
15 VSS
17 DQ3
19 DQ8
21 VDD
23 DQ9
25 DQS1
27 VSS
29 DQ10
31 DQ11
33 VDD
35 CK0
37 /CK0
39 VSS
Key
41 DQ16
43 DQ17
45 VDD
47 DQS2
49 DQ18
51 VSS
53 DQ19
55 DQ24
57 VDD
59 DQ25
61 DQS3
63 VSS
65 DQ26
Pin Front Pin Front Pin Back
67 DQ27 135 DQ34
69 VDD 137 VSS
71 CB0 139 DQ35
73 CB1 141 DQ40
75 VSS 143 VDD
77 DQS8 145 DQ41
79 CB2 147 DQS5
81 VDD 149 VSS
83 CB3 151 DQ42
85 DU 153 DQ43
87 VSS 155 VDD
89 CK2 157 VDD
91 /CK2 159 VSS
93 VDD 161 VSS
95 CKE1 163 DQ48
97 DU(A13) 165 DQ49
99 A12 167 VDD
101 A9 169 DQS6
103 VSS 171 DQ50
105 A7 173 VSS
107 A5 175 DQ51
109 A3 177 DQ56
111 A1 179 VDD
113 VDD 181 DQ57
115 A10/AP 183 DQS7
117 BA0 185 VSS
119 /WE 187 DQ58
121 /S0 189 DQ59
123 DU 191 VDD
125 VSS 193 SDA
127 DQ32 195 SCL
129 DQ33 197 VDDSPD
131 VDD 199 VDDID
133 DQS4
2 VREF
4 VSS
6 DQ4
8 DQ5
10 VDD
12 DM0
14 DQ6
16 VSS
18 DQ7
20 DQ12
22 VDD
24 DQ13
26 DM1
28 VSS
30 DQ14
32 DQ15
34 VDD
36 VDD
38 VSS
40 VSS
Key
42 DQ20
44 DQ21
46 VDD
48 DM2
50 DQ22
52 VSS
54 DQ23
56 DQ28
58 VDD
60 DQ29
62 DM3
64 VSS
66 DQ30
Pin
Back
Pin
68
DQ31 136
70
VDD
138
72
CB4
140
74
CB5
142
76
VSS
144
78
DM8
146
80
CB6
148
82
VDD
150
84
CB7
152
86 DU/(RESET) 154
88
VSS
156
90
VSS
158
92
VDD
160
94
VDD
162
96
CKE0 164
98 DU(BA2) 166
100
A11
168
102
A8
170
104
VSS
172
106
A6
174
108
A4
176
110
A2
178
112
A0
180
114
VDD
182
116
BA1
184
118
/RAS
186
120
/CAS
188
122
/S1
190
124
DU
192
126
VSS
194
128 DQ36 196
130 DQ37 198
132
VDD
200
134
DM4
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0~ CK2,
CK0~ CK2
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
SCL
SA0 ~ 2
VDDID
NC
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 June. 2001

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