M48T35-70PC1 查看數據表（PDF） - STMicroelectronics
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M48T35-70PC1 Datasheet PDF : 18 Pages
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M48T35, M48T35Y
Table 11. Register Map
Data
Address
D7
D6
D5
D4
D3
D2
D1
D0
7FFFh
10 Years
Year
7FFEh
0
0
0
10 M
Month
7FFDh
0
0
10 Date
Date: Day of Month
7FFCh
0
FT
CEB
CB
0
Day of Week
7FFBh
0
0
10 Hours
Hours (24 Hour Format)
7FFAh
0
10 Minutes
Minutes
7FF9h
ST
10 Seconds
Seconds
7FF8h
W
R
S
Calibration
Function/Range
BCD Format
Year
00-99
Month
01-12
Date
01-31
Century/Day 00-01/01-07
Hour
00-23
Minutes
00-59
Seconds
00-59
Control
Keys: S = Sign Bit
FT = Frequency Test Bit (Must be set to ‘0’ upon power for normal operation)
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
CEB = Century Enable Bit
CB = Century Bit
Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of the century (dependent upon the initial value set).
When CEB is set to ‘0’, CB will not toggle.
The WRITE Bit does not need to be set to write to CEB and CB.
CLOCK OPERATIONS
Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPORT TIMEKEEPER cells in the RAM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Setting the Clock
Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting the WRITE bit to a ’1’, like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 11). Resetting the WRITE bit to a ’0’ then
transfers the values of all time registers 7FF9h-
7FFFh to the actual TIMEKEEPER counters and
allows normal operation to resume.The FT bit and
the bits marked as ’0’ in Table 11 must be written
to ’0’ to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next
clock update will occur within one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" on the for information
on Century Rollover.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T35/35Y is
shipped from STMicroelectronics with the STOP
bit set to a ’1’. When reset to a ’0’, the M48T35/35Y
oscillator starts within 1 second.
Calibrating the Clock
The M48T35/35Y is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 ppm
(parts per million) oscillator frequency error at
25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T35/35Y improves to better
than ±4 ppm at 25 °C. The oscillation rate of any
crystal changes with temperature (see Figure 10).
10/18
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