M48T512V 查看數據表（PDF） - STMicroelectronics

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M48T512V

5.0 or 3.3V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T512Y, M48T512V*

Data Retention Mode

With valid VCC applied, the M48T512Y/V operates

as a conventional BYTEWIDE™ static RAM.

Should the supply voltage decay, the RAM will au-

tomatically deselect, write protecting itself when

VCC falls between VPFD (max), VPFD (min) win-

dow. All outputs become high impedance and all

inputs are treated as “Don't care.”

Note: A power failure during a WRITE cycle may

corrupt data at the current addressed location, but

does not jeopardize the rest of the RAM's content.

At voltages below VPFD (min), the memory will be

in a write protected state, provided the VCC fall

time is not less than tF. The M48T512Y/V may re-

spond to transient noise spikes on VCC that cross

into the deselect window during the time the de-

vice is sampling VCC.Therefore, decoupling of the

power supply lines is recommended. When VCC

drops below VSO, the control circuit switches pow-

er to the internal battery, preserving data and pow-

ering the clock. The internal energy source will

maintain data in the M48T512Y/V for an accumu-

lated period of at least 10 years at room tempera-

ture. As system power rises above VSO, the

battery is disconnected, and the power supply is

switched to external VCC. Write protection contin-

ues until VCC reaches VPFD (min) plus tREC (min).

Normal RAM operation can resume tREC after VCC

exceeds VPFD (max). Refer to Application Note

(AN1012) on the ST Web Site for more information

on battery life.

10/21

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