M48T512V 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M48T512V

5.0 or 3.3V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T512Y, M48T512V*

WRITE Mode

The M48T512Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are low

state after the address inputs are stable.

The start of a WRITE is referenced from the latter

occurring falling edge of W or E. A WRITE is termi-

nated by the earlier rising edge of W or E. The ad-

dresses must be held valid throughout the cycle. E

or W must return high for a minimum of tEHAX from

Chip Enable or tWHAX from WRITE Enable prior to

the initiation of another READ or WRITE cycle.

Data-in must be valid tDVWH prior to the end of

WRITE and remain valid for tWHDX afterward. G

should be kept high during WRITE cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G a low on W will

disable the outputs tWLQZ after W falls.

Figure 6. WRITE AC Waveforms, WRITE Enable Controlled

A0-A18

E

tAVEL

tAVWL

tAVAV

VALID

tAVWH

tWLWH

tWHAX

W

DQ0-DQ7

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI02386

Figure 7. WRITE AC Waveforms, Chip Enable Controlled

tAVAV

A0-A18

VALID

tAVEL

tAVEH

tELEH

E

tAVWL

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

AI02387

8/21

Share Link: