M48Z08MH 查看數據表（PDF） - STMicroelectronics
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M48Z08MH Datasheet PDF : 18 Pages
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M48Z08
M48Z18
64 Kbit (8Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z08: 4.50V ≤ VPFD ≤ 4.75V
– M48Z18: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28 LEAD SOIC
and SNAPHAT® TOP (to be Ordered
Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
PIN and FUNCTION COMPATIBLE with the
DS1225 and JEDEC STANDARD 8K x 8
SRAMs
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z08/18 ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM which is pin and func-
tional compatible with the DS1225. The monolithic
chip is available in two special packages to provide
a highly integrated battery backed-up memory so-
lution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
VCC
13
A0-A12
W
E
G
M48Z08
M48Z18
8
DQ0-DQ7
VSS
AI01022
March 1999
1/18
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