M48Z129VPM 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
M48Z129VPM Datasheet PDF : 13 Pages
| |||
Table 3. Operating Modes (1)
Mode
VCC
E
G
Deselect
Write
Read
Read
4.5V to 5.5V
(M48Z129Y)
or
3.0V to 3.6V
(M48Z129V)
VIH
X
VIL
X
VIL
VIL
VIL
VIH
Deselect
VSO to VPFD (min) (2)
X
X
Deselect
≤ VSO (2)
X
X
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Figure 3. Block Diagram
M48Z129Y, M48Z129V
W
DQ0-DQ7
X
High Z
VIL
DIN
VIH
DOUT
VIH
High Z
X
High Z
Power
Standby
Active
Active
Active
CMOS Standby
X
High Z Battery Back-up Mode
VCC
POWER
131,072 x 8
E
VOLTAGE SENSE
SRAM ARRAY
AND
SWITCHING
CIRCUITRY
E
INTERNAL
BATTERY
RST BL
VSS
A0-A16
DQ0-DQ7
W
G
AI03608
WRITE MODE
The M48Z129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are active.
The start of a write is referenced from the latter oc-
curring falling edge of W or E. A write is terminat-
ed by the earlier rising edge of W or E. The
addresses must be held valid throughout the cycle.
E or W must return high for a minimum of tEHAX
from Chip Enable or tWHAX from Write Enable prior
to the initiation of another read or write cycle.
Data-in must be valid tDVWH prior to the end of
write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W
will disable the outputs tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48Z129Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as “don’t care”.
3/13
Share Link: 