M48Z08(2010) 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
M48Z08 Datasheet PDF : 20 Pages
| |||
Operation modes
M48Z08, M48Z18
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z08/M48Z18
Unit
Min
Max
tAVAV WRITE cycle time
100
ns
tAVWL Address valid to WRITE enable low
0
ns
tAVEL Address valid to chip enable 1 low
0
ns
tWLWH WRITE enable pulse width
80
ns
tELEH Chip enable low to chip enable 1 high
80
ns
tWHAX WRITE enable high to address transition
10
ns
tEHAX Chip enable high to address transition
10
ns
tDVWH Input valid to WRITE enable high
50
ns
tDVEH Input valid to chip enable 1 high
30
ns
tWHDX WRITE enable high to input transition
5
ns
tEHDX Chip enable high to input transition
5
ns
tWLQZ(2)(3) WRITE enable low to output Hi-Z
50
ns
tAVWH Address valid to WRITE enable high
80
ns
tAVEH Address valid to chip enable high
80
ns
tWHQX(2)(3) WRITE enable high to output transition
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. CL = 30 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
Data retention mode
With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z08/18 may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z08/18 for an
accumulated period of at least 11 years when VCC is less than VSO.
As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write protection continues until VCC reaches VPFD
(min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume trec
after VCC exceeds VPFD (max). For more information on battery storage life refer to the
application note AN1012.
10/20
Doc ID 2424 Rev 7
Share Link: 