M48Z58-70MH1 查看數據表（PDF） - STMicroelectronics
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M48Z58-70MH1 Datasheet PDF : 17 Pages
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M48Z58
M48Z58Y
64 Kbit (8Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z58: 4.50V ≤ VPFD ≤ 4.75V
– M48Z58Y: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z58/58Y ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
March 1999
VCC
13
A0-A12
8
DQ0-DQ7
W
M48Z58
M48Z58Y
E
G
VSS
AI01176B
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