M48Z35PC 查看數據表（PDF） - STMicroelectronics
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M48Z35PC Datasheet PDF : 23 Pages
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Operating modes
M48Z35, M48Z35Y
2.2
Write mode
The M48Z35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. Write enable controlled, write AC waveforms
A0-A14
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI00926
Figure 7. Chip enable controlled, write AC waveforms
A0-A14
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
AI00927
10/23
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