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M52334 查看數據表(PDF) - MITSUBISHI ELECTRIC

零件编号
产品描述 (功能)
生产厂家
M52334
Mitsubishi
MITSUBISHI ELECTRIC  Mitsubishi
M52334 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MITSUBISHI ICs (TV)
M52334FP
PLL-SPLIT VIF/SIF IC
µ AFT sensitivity, V19H AFT maximum voltage,
V19L AFT minimum voltage
1. Input SG10 into VIF IN, and set the frequency of SG10 so that
the voltage of AFT output TP19 is 5V. This frequency is named
f(3).
2. Set the frequency of SG10 so that the AFT output voltage is 4V.
This frequency is named f (2)
3. IN the graph, maximum and minimum DC voltage are V19H and
V19L, respectively.
TP19
Voltage
5V
V19H
4V
V19L
f (3)
f (2)
f (MHz)
1000 (mV)
µ=
f (2) - f (3) (kHz)
(mV/kHz)
IM Intermodulation
1. Input SG11 into VIF IN, and measure EQ output TP3A with an
oscilloscope.
2. Adjust AGC filter voltage V13 so that the minimum DC level of
the output waveform is 1.0V.
3. At this time, measure, TP3A with a spectrum analyzer.
The intermodulation is defined as a difference between 0.92MHz
and 3.58MHz frequency components.
LIM Limiting sensitivity
1. Input SG17 (Vi=90dBµ) into SIF input, and measure the 400Hz
component level of AF output TP11.
2. Lower the input level of SG17, and measure the level of SG17
when the VoAF level reaches -3dB.
AMR AM Rejection
1. Input SG18 into SIF input, and measure the output level of AF
output TP11. This level is named VAM.
2. AMR is;
VoAF (mVr.m.s)
AMR=20log
(dB)
VAM (mVr.m.s)
AF S/N
1. Input SG19 into SIF input, and measure the output noise level of
AF output TP11. This level is named VN.
2. S/N is;
VoAF (mVr.m.s)
S/N=20log
(dB)
VN (mVr.m.s)
THE NOTE IN THE SYSTEM SETUP
M52334FP has 2 power supply pins of Vcc (pin 7) and Vreg. OUT
(pin 4). Pin 7 is for AFT output, RF AGC output circuits and 5V
regulated power supply circuit and Pin 4 is for the other circuit
blocks. In case M52334FP is used together with other ICs like VIF
operating at more than 5V, the same supply voltage as that of
connected ICs is applied to VCC and Vreg. Out is opened. The other
circuit blocks, connected to Vreg. OUT are powered by internal 5V
regulated power supply.
In case the connecting ICs are operated at 5V, 5V is supplied to
both VCC and Vreg.OUT.
INPUT SIGNAL
SG No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Signals (50termination)
f0=45.75MHz AM20kHz 77.8% 90dBµ
f0=45.75MHz 90dBµ CW
f1=45.75MHz 90dBµ CW (Mixed signal)
f2=Frequency variable 70dBµ CW (Mixed signal)
f0=45.75MHz AM20kHz 77.8% level variable
f0=45.75MHz AM20kHz 14.0% level variable
f0=45.75MHz 80dBµ CW
f0=45.75MHz 110dBµ CW
f0=45.75MHz CW level variable
f0=Variable AM20kHz 77.8% 90dBµ
f0=Variable 90dBµ CW
f1=45.75MHz 90dBµ CW (Mixed signal)
f2=42.17MHz 80dBµ CW (Mixed signal)
f3=41.25MHz 80dBµ CW (Mixed signal)
f0=45.75MHz 87.5%
TV modulation ten-step waveform
Sync tip level 90dBµ
f1=41.25MHz 103dBµ CW
f1=41.25MHz 70dBµ CW
f1=45.75MHz 90dBµ CW (Mixed signal)
f2=41.25MHz 70dBµ CW (Mixed signal)
f0=4.5MHz 90dBµ FM400Hz±25kHz dev
f0=4.5MHz FM400Hz±25kHz dev level variable
f0=4.5MHz 90dBµ AM400Hz 30%
f0=4.5MHz 90dBµ CW
4

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