M54HC138_ 查看數據表（PDF） - STMicroelectronics

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M54HC138_

RAD HARD 3 TO 8 LINE DECODER (INVERTING)

STMicroelectronics 

M54HCT138

RAD HARD 3 TO 8 LINE DECODER (INVERTING)

s HIGH SPEED:

tPD = 16ns (TYP.) at VCC = 4.5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN.) VIL = 0.8V (MAX)

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 138

s DEVICE FULLY COMPLIANT WITH

SCC-9205-022

DESCRIPTION

The M54HCT138 is an high speed CMOS 3 TO 8

LINE DECODER fabricated with silicon gate

C2MOS technology.

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

DILC-16

FPC-16

ORDER CODES

PACKAGE

FM

DILC

FPC

M54HC138D

M54HC138K

EM

M54HC138D1

M54HC138K1

inhibited and all the 8 outputs go high. Three

enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION

June 2004

Rev. 1

1/10

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