M58BF008 查看數據表（PDF） - STMicroelectronics
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M58BF008 Datasheet PDF : 36 Pages
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M58BF008
ORGANISATION
The M58BF008 has a data path width of 32 bit
(Double-Word) and is organised as a Main memo-
ry array of 32 blocks of 256 Kbit plus an Overlay
block of 256 Kbit having the same address space
as the first Main memory block. The memory map
is shown in Table 3.
The memory is addressed by A0-A17 which are
static for Asynchronous or latched for Synchro-
nous operation. Data Input/Output is static or
latched on DQ0-DQ31, these signals output data,
Table 3. Block Addresses
#
Size
(Kbit)
31
256
30
256
29
256
28
256
27
256
26
256
25
256
24
256
23
256
22
256
21
256
20
256
19
256
18
256
17
256
16
256
15
256
14
256
13
256
12
256
11
256
10
256
9
256
8
256
7
256
6
256
5
256
4
256
3
256
2
256
1
256
0
256
Overlay Block
256
Address Range
3E000-3FFFF
3C000-3DFFF
3A000-3BFFF
38000-39FFF
36000-37FFF
34000-35FFF
32000-33FFF
30000-31FFF
2E000-2FFFF
2C000-2DFFF
2A000-2BFFF
28000-29FFF
26000-27FFF
24000-25FFF
22000-23FFF
20000-21FFF
1E000-1FFFF
1C000-1DFFF
1A000-1BFFF
18000-19FFF
16000-17FFF
14000-15FFF
12000-13FFF
10000-11FFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
00000-01FFF
status or signatures read from the memory, or they
input data to be programmed or Instruction com-
mands to the Command Interface.
Asynchronous mode
Memory control is provided by Chip Enable E, Out-
put Enable G and Write Enable W for read and
write operations.
Synchronous mode
Memory control is provided by Load Burst Address
LBA which loads a read or write address. A Syn-
chronous Single Read or a Synchronous Burst
Read is performed under control of Output Enable
G. Synchronous Write is controlled by Write/Read
Enable WR, Load Burst Address LBA and Write
Enable W. Internal advance of the burst address is
controlled by Burst Address Advance BAA.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17). The address signal
A17 is the MSB and A0 the LSB.
In the Asynchronous mode the addresses must be
stable before Chip Enable E and Write Enable W
go to VIL. They must remain stable during the read
or write cycle.
In the Synchronous modes, the addresses are
latched by the rising edge of the System Clock
CLK when both Latch Burst Address LBA and
Chip Enable E are at VIL. The addresses are
latched for a read operation if Write/Read WR is at
VIH or for a write operation when it is at VIL.
Data Input/Output (DQ0-DQ31). The data signal
DQ31 is the MSB and DQ0 the LSB. Commands
are input on DQ0-DQ7.
Data input is a Double-Word to be programmed in
the memory or an Instruction command to the
Command Interface. Data is read from the Main or
Overlay memory blocks, the Status Register or the
Electronic Signature.
In the Asynchronous mode data is read when the
addresses are stable and Chip Enable E and Out-
put Enable G are at VIL. Commands or address/
data are written when Chip Enable E and Write W
are at VIL.
In the Synchronous mode, after addresses are
latched, data is read on a rising edge of the Sys-
tem Clock CLK when Chip Enable E is at VIL and
if Output Enable was at VIL on the previous rising
clock edge. Data is written on a rising edge of the
System Clock CLK when Chip Enable E and Write
Enable W are at VIL.
The outputs are high impedance when Chip En-
able E or Output Enable G are at VIH, or when Out-
put Disable GD is at VIL. Outputs are also high
impedance when System Reset RP is at VIL.
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