M58BF008ZA 查看數據表（PDF） - STMicroelectronics

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M58BF008ZA

8 Mbit (256Kb x32, Burst) Flash Memory

STMicroelectronics 

M58BF008

– Synchronous Single Read. To read a single

data Double-Word in Synchronous mode Chip

Enable E must be Low. Load Burst Address

LBA must be Low for one System Clock CLK ris-

ing edge with Write/Read WR High. This latches

the read address, after which the address bus

inputs are Don’t Care. The Output Enable G is

Low for a single System Clock CLK cycle. The

Double-Word of valid data is output on the next

System Clock CLK rising edge.

– Synchronous Burst Read. To read a burst of

four Double-Words in Synchronous mode Chip

Enable /E must be Low. Load Burst Address

LBA must be Low for one System Clock CLK ris-

ing edge with Write/Read WR High. This latches

the first address of the burst sequence, after

which the address bus inputs are Don’t Care.

The Output Enable G is driven Low before the

burst output sequence. Four Double-Words of

data are output on the subsequent System

Clock CLK rising edges if Burst Address Ad-

vance BAA is maintained Low. The address ad-

vance for synchronous burst read is suspended

if Burst Address Advance BAA goes High and

the output data remains constant. The data bus

will go high impedance on the rising edge of the

System Clock CLK after Output Enable G goes

High.

The burst timing depends on the device config-

uration for the Critical Word X and Burst Word Y

latency times and the choice of wrap or no-wrap

for burst addresses. The operation burst wrap is

shown in Table 13. The wrap sequence uses

only the address bits A0 and A1 and does not

repeat after the last Double-Word has been out-

put.

Read Overlay Block. The Overlay block can be

read, as for a Main block, after it has been en-

abled. To enable the Overlay block the Overlay

Block Enable bit OBEB and the Overlay Block Sta-

tus bit OBS in the Status Register must be set to

’1’ - see Table 9.

The Overlay Block Enable bit OBEB can be set to

’1’ in three ways - see Table 10:

– By Toggling the Reset/Power-Down signal RP

with the VPP Program/Erase supply in the range

VPP1 or VPPH. VPP out of range will reset the

OBEB bit to ’0’.

– By a leaving power-on reset with VPP Program/

Erase supply in the range VPP1 or VPPH. VPP out

of range will reset the OBEB bit to ’0’.

– By giving the Overlay Block Enable/Disable for

Read Instruction OBT.

The Overlay Block Status bit OBS monitors the

VPP Program/Erase supply and will be set to ’1’

when in the range VPP1 or VPPH. The Overlay

block is enabled with OBEB at ’1’ but will not be

read unless OBS status bit is also at ’1’. If it is not

8/36

then a read operation will read the contents of the

Main block at the same address.

When the Overlay block is enabled for reading,

only this one block of 256 Kbit is accesible and

none of the other Main blocks may be accessed,

the address signals A13-A17 are Don’t Care.

Read Electronic Signature. The memory con-

tains three Electronic Signature codes identifying

the manufacturer, device and version, which can

be read after giving the Instruction RSIG. The

manufacturer code 00000020h is read when the

address inputs A0 and A1 are at VIL. The device

code 000000F0h is read when A0 is at VIH and A1

is at VIL. The version code 0000000xh is read

when A0 is at VIL and A1 is at VIH. The codes are

read on DQ0-DQ31, all other address signal inputs

are Don’t Care. See Table 5.

Write. Write operations are used to give com-

mands to the memory that latch input data and ad-

dresses to program or block addresses to erase.

– Asynchronous Write. To write data in the

Asynchronous mode the address inputs must

be stable and Chip Enable E must be Low dur-

ing the write cycle. Write W must be Low and in-

put data valid on the rising edge is Write W.

– Synchronous Write. To write input data in

Synchronous mode Chip Enable E must be

Low. Load Burst Address LBA must be Low for

one System Clock CLK rising edge with Write/

Read WR Low. This latches the write address,

after which the address bus inputs are Don’t

Care. When Write Enable W is Low input data is

latched on the next System Clock CLK rising

edge.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High or

when the Output Disable GD is Low, independent

of the level on Output Enable G.

Standby. The memory is in standby when the P/

E.C. is not running, the memory is in read mode

and Chip Enable E is High. The power consump-

tion is reduced to the standby level and the outputs

are high impedance, independent of the Output

Enable G or Write Enable W inputs.

If Chip Enable goes High during a program or

erase operation the device enters the standby

mode when the internal algorithm has finished.

Reset/Power-down. During power-down all in-

ternal circuits are switched off, the memory is de-

selected and the outputs are high impedance. The

memory is in Power-down mode when Reset/Pow-

er-down RP is Low. The power consumption is re-

duced to the power-down level, independent of the

Chip Enable E, Load Burst Address LBA, Output

Enable G or Write Enable W inputs.

If Reset/Power-down RP is pulled Low during a

program or erase operation this is aborted and the

memory content is no longer valid.

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