M58LW064 查看數據表（PDF） - STMicroelectronics

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M58LW064

64 Mbit (x16 and x16/x32, Block Erase) Low Voltage Flash Memories

STMicroelectronics 

M58LW064A, M58LW064B

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A1-A22). A1 is used to select

between the high and low Word in the x16 config-

uration of the M58LW064A or B. For the

M58LW064B A1 is not used in the x32 mode.

When Chip Enable E is at VIL the address bus is

used to input addresses for the memory array in

Read mode, or addresses for the data to be pro-

grammed, or to input addresses associated with

Commands to be written to the Command Inter-

face. The address latch is transparent when Latch

Enable L is at VIL. The address inputs for the

memory array are latched on the rising edge of

Chip Enable E or Latch Enable L or Write Enable

W, whichever occurs first in a write operation. The

address is also internally latched in the command

for an Erase or Program Instruction.

Data Inputs/Outputs (DQ0-DQ31). Input data

for a Write to Buffer and Program operation and for

writing Commands to the Command Interface are

latched on the rising edge of Write Enable W or

Chip Enable E, whichever occurs first.

When Chip Enable E and Output Enable G are at

VIL data is output from the Array, the Electronic

Signature - the Manufacturer and the Device code

- the Block Protection status, the CFI Query infor-

mation or the Status Register. The data bus is high

impedance when the device is deselected with

Chip Enable E at VIH, Output Enable G is at VIH or

RP is at VIL. When the P/E.C. is active the Status

Register content is output on DQ0-DQ7 and DQ8-

DQ31 are at VIL.

Chip Enable (E). The Chip Enable E input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable E at VIH

deselects the memory and reduces the power con-

sumption to the standby level.

Output Enable (G). The Output Enable G gates

the outputs through the data output buffers during

a read operation. When Output Enable G is at VIH

the outputs are high impedance. Output Enable G

can be used to suspend the data output in a burst

read operation.

Write Enable (W). The Write Enable W input

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data are latched on the rising edge of W (see also

Latch Enable L).

Reset/Power-down (RP). The Reset/Power-

down RP input provides a hardware reset of the

memory and power-down functions. Reset/Power-

down of the memory is achieved by pulling RP to

VIL for at least tPLPH. Writing is inhibited to protect

data, the Command Interface and the P/E.C. are

reset. The Status Register information is cleared

and power consumption is reduced to deep power-

down level. The device acts as deselected, that is

the data outputs are high impedance.

When RP rises to VIH, the device will be available

for new operations after a delay of tPHQV and will

be configured by default for Asynchronous Ran-

dom Read. The minimum delay required to access

the Command Interface by a write cycle is tPHWL.

If the RP input is activated during a Block Erase, a

Write to Buffer and Program or a Block Protect/Un-

protect operation the cycle is aborted and data is

altered and may be corrupted. The Ready/Busy

output RB may remain low for a maximum time of

tPLPH + tPHRH beyond the completion of the Reset/

Power-down RP pulse.

Applying the higher voltage VHH to the Reset/Pow-

er-down input RP temporarily unprotects and en-

ables Erase and Program operations on all blocks.

Thus it acts as a hardware block unprotect input.

In an application, it is recommended to associate

RP to the reset signal of the microprocessor. Oth-

erwise, if a reset operation occurs while the device

is performing an Erase or Program cycle, the

Flash memory may output the Status Register in-

formation instead of being re-initialized to the de-

fault Asynchronous Random Read.

Latch Enable (L). Latch Enable L latches the ad-

dress bits A1-A22 on its rising edge for the Asyn-

chronous Latch Enable Controlled Read or Write,

or Synchronous Burst Read operations. The ad-

dress latch is transparent when Latch Enable L is

at VIL. Latch Enable L must remain at VIL for Asyn-

chronous Random Read and Write operations.

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