M58LW064 查看數據表（PDF） - STMicroelectronics

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M58LW064

64 Mbit (x16 and x16/x32, Block Erase) Low Voltage Flash Memories

STMicroelectronics 

M58LW064A, M58LW064B

DEVICE OPERATIONS

See Tables 5, 6, 7 and 10.

Address Latch. An address is latched on the ris-

ing edge of the Latch Enable L input for Asynchro-

nous Latch Enable Controlled Read. For

Asynchrouns Latch Enable Controlled Write, the

address is latched on the rising edge of Chip En-

able E, Write Enable W or Latch Enable L, which-

ever occurs first.

For Synchronous Burst Read the address is

latched on the first valid Burst Clock K edge when

Latch Enable L is at Low, or on the rising edge of

Latch Enable L, whichever occurs first.

Asynchronous Random Read. Asynchronous

Random Read outputs the contents of the Array.

Both Chip Enable E and Output Enable G must be

Low in order to read the output of the memory.

By first writing the appropriate Instruction, the

Electronic Signature (RSIG), the Status Register

(RSR), the Read Query Instruction (RCFI) or the

Block Protection Status (RSIG) can be read.

Asynchronous Random Read is the default read

mode which the device enters on power-up or on

return from Reset/Power-down.

Asynchronous Page Read. Asynchronous

Page Read may be used for Random or Latch En-

able Controlled Reads of the Array, which are per-

formed independent of the Burst Clock signal. A

page has a size of 4 Words or 2 Double-Words

and is addressed by the address inputs A1 and A2

in the x16, or A2 only in the x32 organisation. Data

is read internally and stored in the Page Buffer.

The page read starts when both Chip Enable E

and Output Enable G are Low. The first data is in-

ternally read and is output after the normal access

time tAVQV. Successive Words or Double-Words

can be read with a much reduced access time of

tAVQV1 by changing only the low address bits.

Synchronous Burst Read. The memory sup-

ports different types of burst access using a Burst

Configuration Register to configure the burst type,

length and latency.

In continuous burst read, one burst read operation

can access the entire memory sequentially by

keeping the Burst Address Advance B Low for the

appropriate number of clock cycles. At the end of

the memory address space the burst read restarts

from the beginning at address 000000h.

Synchronous Burst Read is activated when the

Burst Clock K input is clocking and Chip Enable E

is Low. The burst start address is latched and

loaded into the internal Burst Address Counter on

the valid Burst Clock K edge (rising or falling de-

pending on the M6 bit value for the Burst Clock

Edge Configuration in the Burst Configuration

Register) when Latch Enable L is Low, or upon the

rising edge of Latch Enable L when the Burst

Clock K is valid. After an initial memory latency

time, the memory outputs data each clock cycle

(or two clock cycles depending on M9 bit value de-

fined in the Burst Configuration Register). The

Burst Address Advance B input controls the mem-

ory burst output. The second burst output is on the

next clock valid edge after the Burst Address Ad-

vance B has been pulled Low.

The Valid Data Ready output signal R monitors if

the memory burst boundary is exceeded and the

Burst Controller of the microprocessor needs to in-

sert wait states. When Valid Data Ready R is Low

on the active clock edge, no new data is available

and the memory does not increment the internal

address counter at the active clock edge even if

Burst Address Advance B is Low.

Synchronous Burst Read will be suspended when

Burst Address Advance B is High. The Valid Data

Ready signal R may be configured (by bit M8 of

Burst Configuration Register) to be valid immedi-

ately at the valid clock edge or one data cycle be-

fore the valid clock edge.

To increase the data throughput the device has

been built with an internal pipelined architecture

allowing the user to enter a burst read input com-

mand and the next starting address location to be

read while the device is filling the output data bus

with its current burst content. This pipelined struc-

ture is intended to produce no wait-states on the

output data bus for successive burst read mode

operations.

Asynchronous and Latch Enable Controlled

Write. Asynchronous Write is used to give com-

mands to the Command Interface for Instructions

to the memory or to latch addresses and input data

to be programmed. To perform any Instruction the

Command Interface is activated starting with a

write cycle. A write cycle is also required give the

Instruction to clear the Status Register informa-

tion. Two write cycles are needed to define the

Block Erase and the Write to Buffer and Program

Instructions. The first write cycle defines the In-

struction selection and the second indicates the

appropriate block address to be erased for the

Block Erase instruction, or the address locations to

program with the number of Words or Double-

Words in the Write to Buffer and Program Instruc-

tion.

An Asynchronous Write is initiated when Chip En-

able E, Write Enable W and Latch Enable L are

Low with Output Enable G High. Commands and

Input Data are latched on the rising edge of Chip

Enable E or Write Enable W, whichever occurs

first. For an Asynchronous Latch Enable Con-

trolled Write the address is latched on the rising

edge of Latch Enable L, Write Enable W or Chip

Enable E, whichever occurs first.

12/53

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