M58LW064 查看數據表（PDF） - STMicroelectronics

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M58LW064

64 Mbit (x16 and x16/x32, Block Erase) Low Voltage Flash Memories

STMicroelectronics 

M58LW064A, M58LW064B

Data to be programmed in the array is internally

latched in the Write Buffer before the programming

operation starts and a minimum of 4 Words or 2

Double-Words need to be programmed in the

same sequence and must be contained in the

same address location boundary defined by A1 to

A2 for the x16 and A2 for the x32 organisation.

Write operations are asynchronous and the Burst

Clock signal K is ignored during a write operation.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High.

Standby. The memory is in standby when Chip

Enable E goes High and the P/E.C. is idle. The

power consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable G or Write Enable W inputs.

Automatic Low Power. After a short time of bus

inactivity (no Chip Enable E, Latch Enable L or Ad-

dress transitions) the chip automatically enters a

pseudo-standby mode where consumption is re-

duced to the Automatic Low Power standby value,

while the outputs may still drive the bus. The Auto-

matic Low Power feature is available only for

Asynchronous Read.

Power-down. The memory is in Power-down

when Reset/Power-down RP is Low. The power

consumption is reduced to the power-down level

and the outputs are high impedance, independent

of the Chip Enable E, Output Enable G or Write

Enable W inputs.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory allowing programming equipment or ap-

plications to automatically match their interface to

the characteristics of the memory. The Electronic

Signature is output by giving the RSIG Instruction.

The manufacturer code is output when all the Ad-

dress inputs are Low. The device code is output

when A1 (M58LW064A) or A2 (M58LW064B) in-

put is High, the other pins A3-A22 must be Low.

The codes are output on DQ0-DQ7. A return to

Read mode is achieved by writing the Read Array

instruction.

INITIALIZATION

The device must be powered up and initialized in

a predefined manner. Procedures other than

specified may result in undefined operation.

Power should be applied simultaneously to VDD

and VDDQ with the RP input held Low. When the

supplies are stable RP is taken High. The Output

Enable G, Chip Enable E and Write Enable W in-

puts should also be held High during power-up.

The memory will be ready to accept the first In-

struction after the power-up time tPUR. The device

is automatically configured for Asynchronous Ran-

dom Read at power-up or after leaving Reset/

Power-down.

BURST CONFIGURATION REGISTER

See Tables 8, 9, 10 and 11.

The Synchronous Burst Read, Asynchronous

Random Read, Asynchronous Latch Enable Con-

trolled Read are selected using the Burst Configu-

ration Register.

For Synchronous Read the register defines the X

and Y Latencies, Valid Data Ready signal timing,

Burst Type, Valid Clock Edge and Burst Length.

The Burst Configuration Register is programmed

using the Set Burst Configuration Register (SBCR)

Instruction and will retain the stored information

until it is programmed again or the device is reset

or goes into the Reset/Power-down.

The Burst Configuration Register bits M2-M0

specify the burst length (1, 2, 4, 8 or continuous);

bit M3 specifies Asynchronous Random Read or

Asynchronous Latch Enable Controlled Read; bits

M4 and M5 are not used; bit M6 specifies the rising

or falling burst clock edge as valid; bit M7 specifies

the burst type (Sequential or Interleaved); M8

specifies the Valid Data Ready output period; bit

M9 specifies the Y-latency; bit M10 is not used;

M14-M11 specify the X-latency; and bit M15 se-

lects between Synchronous Burst Read or Asyn-

chronous Read. M10, M5 and M4 are reserved for

future use.

M15 Read Select

The device features three kinds of read operation:

Asynchronous Random Read, Asynchronous

Latch Enable Controlled Read and Synchronous

Burst Read. Page Read may be used in either of

the Asynchronous Read operations.

The Burst Configuration Register bit M15 selects

between Synchronous Burst and Asynchronous

Read.

M14 - M11 and M9 X and Y Latency.

The values of X and Y are used to define the burst

latency for the data sequence. The X-latency de-

fines the number of clock cycles before the output

of the first data from the clock edge that latches

the address. The X-latency can be set from 7 to

16. A value of 7 is only valid for continuous burst.

The Y-latency is the number of clock cycles need-

ed to output the next data from the burst register,

following the first data output. The latency can be

set to 1 or 2 clock cycles.

The minimum X-Latency value to consider de-

pends on the Burst Clock K signal frequency. The

burst performance in terms of frequency is listed in

Table 11 and indicates the minimum X-latency and

Y-latency values (X.Y.Y.Y) related to the burst

type, burst length and x16 or x32 organisation.

13/53

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