M5M5V216ATP-55H 查看數據表（PDF） - Mitsumi
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M5M5V216ATP-55H Datasheet PDF : 7 Pages
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
tCW
A0~16
BC1
and / or
BC2
tsu (A)
tsu (BC1) or
tsu (BC2)
trec (W)
S
(Note3)
(Note5)
W
(Note3)
DQ1~16
Write cycle (S control mode)
A0~16
(Note4)
tsu (D) th (D)
DATA IN
STABLE
tCW
(Note3)
(Note3)
BC1
and / or
BC2
(Note3)
tsu (A)
(Note4)
tsu (S)
trec (W)
(Note3)
S
(Note5)
W
(Note3)
(Note4)
tsu (D) th (D)
(Note3)
DQ1~16
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S low , overlaps BC1 and/or BC2 low and W low.
Note 5: When the falling edge of W is simultaneously or priorto the falling edge of BC1 and/or BC2 or the falling edge of S,
the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
6
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