M5M5W816WG-85HI 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M5M5W816WG-85HI

8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI ELECTRIC  

1999.1.15 Ver. 0.1

MITSUBISHI LSIs

M5M5W816WG -85L, 10L, 85H, 10H

-85LI, 10LI, 85HI, 10HI

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change

8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

Write cycle (BC control mode)

A0~18

BC1,BC2

tsu (A)

tCW

tsu (BC1) or

tsu (BC2)

trec (W)

S1

S2

W

DQ1~16

(Note3)

(Note3)

(Note5)

(Note3)

(Note4)

tsu (D) th (D)

DATA IN

STABLE

(Note3)

(Note3)

(Note3)

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S1 low, S2 high overlaps BC1 and/or BC2 low and W low.

Note 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or the falling edge of S1

or rising edge of S2, the outputs are maintained in the high impedance state.

Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.

MITSUBISHI ELECTRIC

6

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