M5M5Y5672TG-20 查看數據表（PDF） - Renesas Electronics

零件编号

产品描述 (功能)

生产厂家

M5M5Y5672TG-20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Renesas Electronics 

MITSUBISHI LSIs

M5M5Y5672TG – 25,22,20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Read Operation

Pipelined Read

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and

E3) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. The address presented to the address

inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read

access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the

read data is allowed to propagate through the output register and onto the output pins.

CLK

E1#

ADV

W#

BWx#

ADD

DQ

CQ

A

Read A

Deselect

B

Q(A)

Read B

C

D

E

Q(B)

Q(C)

Read C

Read D

Read E

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Preliminary

M5M5Y5672TG REV.0.8

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