M62354P 查看數據表（PDF） - Renesas Electronics
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M62354P Datasheet PDF : 10 Pages
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M62354P/FP/GP
Digital Data Format
Last
First
LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
DAC data
DAC select
data
DAC Data
D0
D1
D2
D3
D4
D5
D6
D7
D/A Output
0
0
0
0
0
0
0
0 (VrefU – VrefL) / 256 × 1 + VrefL
1
0
0
0
0
0
0
0 (VrefU – VrefL) / 256 × 2 + VrefL
0
1
0
0
0
0
0
0 (VrefU – VrefL) / 256 × 3 + VrefL
1
1
0
0
0
0
0
0 (VrefU – VrefL) / 256 × 4 + VrefL
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1 (VrefU – VrefL) / 256 × 255 + VrefL
1
1
1
1
1
1
1
1 VrefU
Note: VrefU = VDD, VrefL = VSS
DAC Select Data
D8
D9
D10
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
D11
0
Don't care
1
AO1 selection
0
AO2 selection
1
AO3 selection
0
AO4 selection
1
AO5 selection
0
AO6 selection
1
Don't care
0
Don't care
1
Don't care
0
Don't care
1
Don't care
0
Don't care
1
Don't care
0
Don't care
1
Don't care
DAC Selection
Timing Chart (Model)
MSB
DI
D11 D10 D9
D8
.............
LSB
D2
D1
D0
CLK
..................
LD
D/A
output
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 6 of 9
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