M68Z512 查看數據表（PDF） - STMicroelectronics
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M68Z512 Datasheet PDF : 12 Pages
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M68Z512
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
VIO (2)
VCC
Storage Temperature
Input or Output Voltage
Supply Voltage
–65 to 150
°C
–0.3 to VCC + 0.3
V
–0.3 to 7.0
V
IO (3)
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Up to a maximum operating VCC of 5.5V only.
3. One output at a time, not to exceed 1 second duration.
Figure 2. TSOP Connections
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
8
M68Z512 25
9
24
16
17
VCC
A15
A18
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI03031
READ MODE
The M68Z512 is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight of the 4,194,304
locations in the static memory array, specified by
the 19 address inputs. Valid data will be available
at the eight output pins within tAVQV after the last
stable address, providing G is Low and E is Low.
If Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (tELQV or tGLQV) rather than the
address. Data out may be indeterminate at tELQX
and tGLQX, but data lines will always be valid at
tAVQV.
WRITE MODE
The M68Z512 is in the Write mode whenever the
W and E pins are Low. Either the Chip Enable in-
put (E) or the Write Enable input (W) must be de-
asserted during Address transitions for subse-
quent write cycles. Write begins with the concur-
rence of Chip Enable being active with W low.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as tAVWL and tAVEH
respectively, and is determined by the latter occur-
ring edge.
The Write cycle can be terminated by the earlier
rising edge of E, or W.
if the Output is enabled (E = Low and G = Low),
then W will return the outputs to high impedance
within tWLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for tDVWH before the ris-
ing edge of Write Enable, or for tDVEH before the
rising edge of E, whichever occurs first, and re-
main valid for tWHDX or tEHDX.
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