M7020R-083ZA1 查看數據表（PDF） - STMicroelectronics

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M7020R-083ZA1

32K x 68-bit Entry NETWORK SEARCH ENGINE

STMicroelectronics 

M7020R

Table 2. Signal Names

Symbol

Type(1)

Description

Clocks and Reset

CLK2X

I Master Clock

PHS_L

I Phase

TEST

I Test Input

RST_L

I Reset

Command and DQ Bus

CMD[8:0]

I Command Bus

CMDV

I Command Valid

DQ[67:0]

I/O Address/Data Bus

ACK(4)

T READ Acknowledge

EOT(4)

T End of Transfer

SSF

T SEARCH Successful Flag

SSV

T

SEARCH Successful Flag

Valid

SRAM Interface

SADR[21:0]

T SRAM Address

CE_L

T SRAM Chip Enable

WE_L

T SRAM Write Enable

OE_L

T SRAM Output Enable

ALE_L

T Address Latch Enable

LHI[6:0]

LHO[1:0]

BHI[2:0]

BHO[2:0]

FULI[6:0]

FULO[1:0]

FULL

ID[4:0]

VDD

VDDQ

TDI

TCK

TDO

TMS

Cascade Interface

I

Local Hit In

O Local Hit Out

I

Block Hit In

O Block Hit Out

I

Full In

O Full Out

O Full Flag

Device Identification

I

Device Identification

Supplies

n/a Chip Core Supply (1.8V)

n/a

Chip I/O Supply (2.5 or

3.3V)

Test Access Port

I

Test Access Port’s Test

Data In

I

Test Access Port’s Test

Clock

T

Test Access Port’s Test

Data Out

I

Test Access Port’s Test

Mode Select

TRST_L

I

Test Access Port’s Reset

Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate

2. “CLK” is an internal clock signal. Any reference to “CLK Cycles” means one cycle of CLK.

3. ACK and EOT Signals require a weak, external pull-down resistor of 47 KΩ or 100 KΩ.

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