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MC80C86 查看數據表(PDF) - Intel

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MC80C86 Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
M80C86 M80C86-2
A C CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Timing Responses
Symbol
Parameter
TCLAV
TCLAX
TCLAZ
TLHLL
TCLLH
TCHLL
TLLAX
TCLDV
TCHDX
TWHDX
TCVCTV
TCHCTV
TCVCTX
TAZRL
TCLRL
TCLRH
TRHAV
TCLHAV
TRLRH
TWLWH
TAVAL
TOLOH
TOHOL
Address Valid Delay
Address Hold Time
Address Float
Delay
ALE Width
ALE Active Delay
ALE Inactive Delay
Address Hold Time
to ALE Inactive
Data Valid Delay
Data Hold Time
Data Hold Time
After WR
Control Active
Delay 1
Control Active
Delay 2
Control Inactive
Delay
Address Float to
READ Active
RD Active Delay
RD Inactive Delay
RD Inactive to Next
Address Active
HLDA Valid Delay
RD Width
WR Width
Address Valid to
ALE Low
Output Rise Time
Output Fall Time
M80C86
Min
Max
10
110
10
TCLAX
80
TCLCHb20
80
85
TCHCLb10
10
110
10
TCLCHb30
10
110
10
110
10
110
0
10
165
10
150
TCLCLb45
10
160
2TCLCLb75
2TCLCLb60
TCLCHb60
15
15
M80C86-2
Min
Max
10
60
10
TCLAX
50
TCLCHb10
50
55
TCHCLb10
10
60
10
TCLCHb30
10
70
10
60
10
70
0
10
100
10
80
TCLCLb40
10
100
2TCLCLb50
2TCLCLb40
TCLCHb40
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
From 0 8V to 2 0V
From 2 0V to 0 8V
NOTES
1 Signal at M82C84A shown for reference only See M82C84A data sheet for the most recent specifications
2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK
3 Applies only to T2 state (5 ns into T3)
11

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