M88 查看數據表（PDF） - STMicroelectronics

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M88

In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems (with CPLD) for MCUs

STMicroelectronics 

M88 FAMILY

The JTAG Serial Interface block allows In-System

Programming (ISP). Embedded dual-bank

memories eliminates the need for an external Boot

EPROM or Flash memory, or an external

programmer. To simplify Flash memory updates,

program execution is performed from a secondary

Flash memory (for the M88xxF2x) or EEPROM

(for the M8813F1x) while the primary Flash

memory is being updated. This solution avoids the

complicated hardware and software overhead

necessary to implement IAP.

ST makes available a software development tool,

PSDsoft, that generates ANSI-C compliant code

for use with your target MCU. This code allows you

to manipulate the non-volatile memory (NVM)

within the FLASH+PSD. Code examples are also

provided for:

– Flash memory IAP via the UART of the host

MCU

– Memory paging to execute code across several

FLASH+PSD memory pages

– Loading, reading, and manipulation of

FLASH+PSD Macrocells by the MCU.

FLASH+PSD ARCHITECTURAL OVERVIEW

FLASH+PSD devices contain several major

functional blocks. Figure 3 shows the architecture

of the M88 FLASH+PSD device family. The

functions of each block are described briefly in the

following sections. Many of the blocks perform

multiple functions and are user configurable.

Memory

The 1 or 2 Mbit (128K x 8, or 256K x 8) Flash

memory is the primary memory of the

FLASH+PSD. It is divided into eight equally-sized

sectors that are individually selectable.

The 256 Kbit (32K x 8) secondary EEPROM or

Flash memory is divided into four equally-sized

sectors. Each sector is individually selectable.

The SRAM is intended for use as a scratch-pad

memory or as an extension to the MCU SRAM. If

an external battery is connected to Voltage Stand-

by (VSTBY, PC2), data is retained in the event of

power failure.

Each sector of memory can be located in a

different address space as defined by the user.

The access times for all memory types includes

the address latching and DPLD decoding time.

The M8813F1x has 64 bytes of OTP memory for

product identifiers, serial numbers, calibration

constants, etc..

Page Register

The 8-bit Page Register expands the address

range of the MCU by up to 256 times. The paged

address can be used as part of the address space

to access external memory and peripherals, or

internal memory and I/O. The Page Register can

also be used to change the address mapping of

sectors of the Flash memories into different

memory spaces for IAP.

PLDs

The device contains two PLDs, the Decode PLD

(DPLD) and the Complex PLD (CPLD), each

optimized for a different function, as shown in

Table 3. The functional partitioning of the PLDs

reduces power consumption, optimizes cost/

performance, and eases design entry.

The DPLD is used to decode addresses and to

generate Sector Select signals for the

FLASH+PSD internal memory and registers. The

DPLD has 17 combinatorial outputs, which are

used to select memory sectors and JTAG. The

CPLD has 16 Output Macrocells (OMC) and 3

combinatorial outputs. The CPLD also has 24

Input Macrocells (IMC) that can be configured as

inputs to the PLDs. The PLDs receive their inputs

from the PLD Input Bus and are differentiated by

their output destinations, number of product terms,

and Macrocells.

The PLDs consume minimal power. The speed

and power consumption of the PLD is controlled

by the Turbo bit in the PMMR0 register and other

bits in the PMMR2 registers. These registers are

set by the MCU at run-time. There is a slight

penalty to PLD propagation time when invoking

the power management features.

I/O Ports

The FLASH+PSD has 27 individually configurable

I/O pins distributed over the four ports (Port A, B,

C, and D). Each I/O pin can be individually

configured for different functions. Ports can be

configured as standard MCU I/O ports, PLD I/O, or

latched address outputs for MCUs using

multiplexed address/data buses. Ports A and B

can be configured to be open drain.

The JTAG pins can be enabled on Port C for In-

System Programming (ISP).

Ports A and B can also be configured as a data

port for a non-multiplexed bus or multiplexed

address/data bus for certain types of 8-bit MCUs.

MCU Bus Interface

FLASH+PSD interfaces easily with most 8-bit

MCUs that have either multiplexed or non-

multiplexed address/data buses. The device is

configured to respond to the MCU’s control

signals, which are also used as inputs to the PLDs.

Where there is a requirement to use a 16-bit data

bus to interface to a 16-bit MCU, two PSDs must

be used. For examples, please see the full data

sheet.

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