AS7C1025A-12TJC 查看數據表（PDF） - Alliance Semiconductor
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AS7C1025A-12TJC Datasheet PDF : 8 Pages
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AS7C1025A
AS7C31025A
®
Read cycle (over the operating range)3,9
-10
-12
-15
-20
Parameter
Symbol Min Max Min Max Min Max Min Max Unit
Read cycle time
tRC
10 – 12 – 15 – 20 –
ns
Address access time
tAA
– 10 – 12 – 15 – 20
ns
Chip enable (CE) access time
tACE
– 10 – 12 – 15 – 20
ns
Output enable (OE) access time
tOE
–3 – 3–4 – 5
ns
Output hold from address change tOH
2– 3 –3– 3 –
ns
CE Low to output in low Z
tCLZ
0– 0 –0– 0 –
ns
CE Low to output in high Z
tCHZ
–3 – 3–4 – 5
ns
OE Low to output in low Z
tOLZ
0– 0 –0– 0 –
ns
OE High to output in high Z
tOHZ
–3 – 3–4 –
5
ns
Power up time
tPU
0– 0 –0– 0 –
ns
Power down time
tPD
– 10 – 12 – 15 – 20
ns
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE and OE controlled)3,6,8,9
CE
tRC1
OE
DOUT
Supply
current
tACE
tCLZ
tPU
tOE
tOLZ
50%
Data valid
tOHZ
tCHZ
tPD
50%
Notes
3
3
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
ICC
ISB
2/6/01; V.0.9
Alliance Semiconductor
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