AS7C256 查看數據表（PDF） - Alliance Semiconductor
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AS7C256 Datasheet PDF : 8 Pages
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AS7C256
AS7C256L
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Data Retention Current
Chip Enable to Data Retention Time
Operation Recovery Time
Input Leakage Current
Symbol
VDR
ICCDR
tCDR
tR
| ILI |
Test Conditions
Min
2.0
VCC = 2.0V
–
CE ≥ VCC–0.2V
0
Vin ≥ VCC–0.2V or
Vin ≤ 0.2V
tRC
–
(L Version Only)
Max
Unit
–
V
150
µA
–
ns
–
ns
1
µA
DATA RETENTION WAVEFORM
(L Version Only)
VCC
4.5V
CEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH
tCDR
Data retention mode
VDR ≥ 2.0V
VDR
4.5V
tR
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AS7C256-07
AC TEST CONDITIONS
– Output load: see Figure B,
except for tCLZ and tCHZ see Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
+3.0V
90%
90%
GND
10%
10%
Figure A: Input Waveform
AS7C256-08
+5V
Dout
255Ω
480Ω
30 pF*
GND
Figure B: Output Load
AS7C256-09
Thevenin Equivalent:
168Ω
Dout
+1.728V
+5V
Dout
255Ω
480Ω
5 pF*
*including scope
and jig capacitance
GND
Figure C: Output Load for tCLZ, tCHZ
AS7C256-10
NOTES
1. During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2. This parameter is sampled and not 100% tested.
3. For test conditions, see AC Test Conditions, Figures A, B, C.
4. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
5. This parameter is guaranteed but not tested.
6. WE is HIGH for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transitioning address.
10. CE or WE must be HIGH during address transitions.
11. All write cycle timings are referenced from the last valid address to the first transitioning address.
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