M93S46-BN3 查看數據表（PDF） - STMicroelectronics

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M93S46-BN3

4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection

STMicroelectronics 

M93S66, M93S56, M93S46

Figure 5. PAWRITE and WRAL Sequence

PAGE

WRITE

PRE

W

S

D

1 1 1 An A0 Dn

Q

ADDR

OP

CODE

CHECK

STATUS

D0

DATA IN

BUSY

READY

WRITE

ALL

PRE

W

S

D

1 0 0 0 1 Xn X0 Dn

CHECK

STATUS

D0

Q

ADDR

OP

CODE

DATA IN

BUSY

READY

AI00890C

Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..

Page Write

A Page Write to Memory (PAWRITE) instruction

contains the first address to be written, followed by

up to 4 data words.

After the receipt of each data word, bits A1-A0 of

the internal address register are incremented, the

high order bits remaining unchanged (A7-A2 for

M93S66, M93S56; A5-A2 for M93S46). Users

must take care, in the software, to ensure that the

last word address has the same upper order ad-

The Page Write to Memory (PAWRITE) instruction

will not be executed if any of the 4 words address-

es the protected area.

Write Enable (W) must be held High before and

during the instruction. Input address and data, on

Serial Data Input (D) are sampled on the rising

edge of Serial Clock (C).

After the last data bit has been sampled, the Chip

Select Input (S) must be taken Low before the next

rising edge of Serial Clock (C). If Chip Select Input

dress bits as the initial address transmitted to

avoid address roll-over.

(S) is brought Low before or after this specific time

frame, the self-timed programming cycle will not

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