M93S46-BN3 查看數據表（PDF） - STMicroelectronics

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M93S46-BN3

4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection

STMicroelectronics 

M93S66, M93S56, M93S46

be started, and the addressed location will not be

programmed.

While the M93Sx6 is performing a write cycle, but

after a delay (tSLSH) before the status information

becomes available, Chip Select Input (S) can be

driven High to monitor the status of the write cycle:

Serial Data Output (Q) is driven Low while the

M93Sx6 is still busy, and High when the cycle is

complete, and the M93Sx6 is ready to receive a

new instruction. The M93Sx6 ignores any data on

the bus while it is busy on a write cycle. Once the

M93Sx6 is Ready, Serial Data Output (Q) is driven

High, and remains in this state until a new start bit

is decoded or the Chip Select Input (S) is brought

Low.

Programming is internally self-timed, so the exter-

nal Serial Clock (C) may be disconnected or left

running after the start of a write cycle.

Write All

The Write All Memory with same Data (WRAL) in-

struction is valid only after the Protection Register

has been cleared by executing a Protection Reg-

ister Clear (PRCLEAR) instruction. The Write All

Memory with same Data (WRAL) instruction simul-

taneously writes the whole memory with the same

data word given in the instruction.

Write Enable (W) must be held High before and

during the instruction. Input address and data, on

Serial Data Input (D) are sampled on the rising

edge of Serial Clock (C).

After the last data bit has been sampled, the Chip

Select Input (S) must be taken Low before the next

rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time

frame, the self-timed programming cycle will not

be started, and the addressed location will not be

programmed.

While the M93Sx6 is performing a write cycle, but

after a delay (tSLSH) before the status information

becomes available, Chip Select Input (S) can be

driven High to monitor the status of the write cycle:

Serial Data Output (Q) is driven Low while the

M93Sx6 is still busy, and High when the cycle is

complete, and the M93Sx6 is ready to receive a

new instruction. The M93Sx6 ignores any data on

the bus while it is busy on a write cycle. Once the

M93Sx6 is Ready, Serial Data Output (Q) is driven

High, and remains in this state until a new start bit

is decoded or the Chip Select Input (S) is brought

Low.

Programming is internally self-timed, so the exter-

nal Serial Clock (C) may be disconnected or left

running after the start of a write cycle.

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