CY7C43644 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C43644

1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644

CY7C43664

CY7C43684

Pin Definitions (continued)

Signal Name Description I/O

Function

FS1/SEN

FS0/SD

Flag Offset

Select

1/Serial

Enable

Flag Offset

Select

0/Serial Data

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register

programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select

the flag offset programming method. Three offset register programming methods are

available: automatically load one of three preset values (8, 16, or 64), parallel load from

I

Port A, or serial load. When serial load is selected for flag offset register programming,

FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.

When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the

X and Y registers. The number of bit writes required to program the offset registers is 40

for the CY7C43644, 48 for the CY7C43664, and 56 for the CY7C43684. The first bit write

stores the Y-register MSB and the last bit write stores the X-register LSB.

MBA

Port A

Mailbox

Select

I A HIGH level on MBA chooses a mailbox register for a Port A read or write

operation. When a read operation is performed on Port A, a HIGH level on MBA selects

data from the Mail2 register for output and a LOW level selects FIFO2 output register data

for output. When a write operation is performed on Port A, a HIGH level on MBA will write

the data into Mail 1 register. While a LOW level will write the data into FIFO1.

MBB

Port B

Mailbox

Select

I A HIGH level on MBB chooses a mailbox register for a Port B read or write

operation. When a read operation is performed on Port B, a HIGH level on MBB selects

data from the Mail1 register for output and a LOW level selects FIFO1 output register data

for output. When a write operation is performed on Port B, a HIGH level on MBB will write

the data into Mail 2 register, while a LOW level will write the data into FIFO2.

MBF1

Mail1

Register Flag

O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1

register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH

by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.

MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2

Mail2

Register Flag

O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2

register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH

by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.

MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

MRS1

FIFO1 Master I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

Reset

memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects

the programming method (serial or parallel) and one of three programmable flag default

offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four

LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur

while MRS1 is LOW.

MRS2

FIFO2 Master I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

Reset

memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects

one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions

of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.

PRS1

FIFO1 Partial

Reset

I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes. During Partial Reset, the

currently selected bus size, endian arrangement, programming method (serial or parallel),

and programmable flag settings are all retained.

PRS2

FIFO2 Partial

Reset

I A LOW on this pin initializes the FIFO2 read and write pointers to the first location

of memory and sets the Port A output register to all zeroes. During Partial Reset,

the currently selected bus size, endian arrangement, programming method (serial or

parallel), and programmable flag settings are all retained.

RT1

Retransmit

I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by

FIFO1

bringing the read pointer back to location zero. The user will still need to perform read

operations to retransmit the data. Retransmit function applies to CY standard mode only.

RT2

Retransmit

I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing

FIFO2

the read pointer back to location zero. The user will still need to perform read operations

to retransmit the data. Retransmit function applies to CY standard mode only.

SIZE

Bus Size

Select

I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW

on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE

to select the bus size and endian arrangement for Port B. The level of SIZE must be static

throughout device operation.

Document #: 38-06022 Rev. *B

Page 5 of 39

Share Link: