MAS9180 查看數據表（PDF） - Micro Analog systems
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MAS9180 Datasheet PDF : 15 Pages
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MAS9180 PAD LAYOUT
DA9180.004
15 September, 2005
VDD
QOP
QOM
QI
AGC
OUT
MAS9180Ax,
x = 1..5 differential input,
B..F asymmetric input
VSS
RFIM
RFIP
PDN
AON
DEC
1474 µm
DIE size = 1.47 x 1.46 mm; PAD size = 80 x 80 µm
Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left
floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
X-coordinate
174 µm
174 µm
174 µm
174 µm
174 µm
175 µm
1295 µm
1295 µm
1295 µm
1295 µm
1295 µm
1282 µm
Y-coordinate
1262 µm
1057 µm
854 µm
648 µm
444 µm
240 µm
225 µm
425 µm
624 µm
825 µm
1039 µm
1200 µm
Note
4
1
2
3
5
5
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
3) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
4) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left
unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.
5) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
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