MAX1421 查看數據表（PDF） - Maxim Integrated
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MAX1421 Datasheet PDF : 17 Pages
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12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA ≥ +25°C guaranteed by production test, TA < +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Differential Reference Voltage
Range
VDIFF (Note 6)
1.024
±10%
V
CML Input Voltage Range
VCML
1.65
±10%
V
REFP Input Voltage Range
VREFP
VCML +
VDIFF / 2
V
REFN Input Voltage Range
VREFN
DIGITAL INPUTS (CLK, CLK, OE, PD)
VCML -
VDIFF / 2
V
Input Logic-High
VIH
0.7 ✕
V
VDVDD
Input Logic-Low
Input Current
Input Capacitance
DIGITAL OUTPUTS (D0–D11)
VIL
CLK, CLK
PD
OE
0.3 ✕
V
VDVDD
±330
-20
+20
µA
-20
+20
10
pF
Output Logic-High
Output Logic-Low
Three-State Leakage
Three-State Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Analog Supply Current with
Internal Reference in Shutdown
Analog Shutdown Current
Digital Supply Current
Digital Shutdown Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
Clock Frequency
Clock High
Clock Low
VOH
VOL
IOH = 200µA
IOL = -200µA
VAVDD
VDVDD
IAVDD
IDVDD
PDISS
PSRR
REFIN = AGND
PD = DVDD
PD = DVDD
Analog power
(Note 9)
fCLK
tCH
tCL
Figure 5
Figure 5, clock period 25ns
Figure 5, clock period 25ns
VDVDD
- 0.5
VDVDD
V
0
0.5
V
-10
+10
µA
2
pF
3.135 3.3 3.465 V
2.7
3.3
3.6
V
52
65
mA
50
63
mA
20
µA
5.5
mA
20
µA
188
214 mW
±1
mV/V
0.1
40.0 MHz
12.5
ns
12.5
ns
4 _______________________________________________________________________________________
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