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MAX199ACAI

Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface

Maxim Integrated 

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_______________Detailed Description

Converter Operation

The MAX199, a multi-range, fault-tolerant ADC, uses

successive approximation and internal input track/hold

(T/H) circuitry to convert an analog signal to a 12-bit

digital output. The parallel-output format provides easy

interface to microprocessors (µPs). Figure 3 shows the

MAX199 in its simplest operational configuration.

Analog-Input Track/Hold

In the internal acquisition control mode (control bit D5

set to 0), the T/H enters its tracking mode on WR’s ris-

ing edge, and enters its hold mode when the internally

timed (6 clock cycles) acquisition interval ends. In bipo-

lar mode, a low-impedance input source, which settles

in less than 1.5µs, is required to maintain conversion

accuracy at the maximum conversion rate.

When configured for unipolar mode, the input does not

need to be driven from a low-impedance source. The

acquisition time (tAZ) is a function of the source output

resistance (RS), the channel input resistance (RIN), and

the T/H capacitance.

Acquisition time is calculated by:

For 0V to VREF: tAZ = 9 x (RS + RIN) x 16pF

For 0V to VREF/2: tAZ = 9 x (RS + RIN) x 32pF

where RIN = 7kΩ, and tAZ is never less than 2µs (0V to

VREF range) or 3µs (0V to VREF/2 range).

In the external acquisition control mode (D5 = 1), the

T/H enters its tracking mode on the first WR rising edge

and enters its hold mode when it detects the second WR

rising edge with D5 = 0. See the External Acquisition

section.

Input Bandwidth

The ADC’s input tracking circuitry has a 5MHz small-

signal bandwidth. When using the internal acquisition

mode with an external clock frequency of 2MHz, a

100ksps throughput rate can be achieved. It is possible

to digitize high-speed transient events and measure

periodic signals with bandwidths exceeding the ADC’s

sampling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended (MAX274/MAX275 continuous-time filters).

Input Range and Protection

Figure 4 shows the equivalent input circuit. The MAX199

can be programmed for input ranges of ±VREF, ±VREF/2,

0V to VREF, or 0V to VREF/2 by setting the appropriate

control bits (D3, D4) in the control byte (see Tables 1 and

2). When an external reference is applied at REFADJ, the

voltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V

< VREF < 4.18V).

µP

CONTROL

INPUTS

1 CLK

DGND 28

100pF

MAX199 VDD 27

2 CS

REF 26

3 WR

REFADJ 25

4 RD

5 HBEN

6 SHDN

7 D7

8 D6

9 D5

10 D4

11 D3/D11

12 D2/D10

13 D1/D9

INT 24

CH7 23

CH6 22

CH5 21

CH4 20

CH3 19

CH2 18

CH1 17

CH0 16

14 D0/D8

15

AGND

0.1µF

+5V

+4.096V

4.7µF

OUTPUT STATUS

ANALOG

INPUTS

µP DATA BUS

Figure 3. Operational Diagram

5.12k

CH_

BIPOLAR

S1

VOLTAGE

REFERENCE

5.12k

UNIPOLAR

OFF

CHOLD

S2

T/H

ON

OUT

HOLD

S3

TRACK

TRACK

S4

HOLD

S1 = BIPOLAR/UNIPOLAR SWITCH

S2 = INPUT MUX SWITCH

S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit

8 _______________________________________________________________________________________

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