MAX3420EECJ(2005) 查看數據表（PDF） - Maxim Integrated

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MAX3420EECJ
(Rev.:2005)

USB Peripheral Controller with SPI Interface

Maxim Integrated 

USB Peripheral Controller

with SPI Interface

Pin Description

PIN

TQFN

TQFP

1

1

2

2

NAME

INPUT/

OUTPUT

FUNCTION

GPOUT0

GPOUT1

Output

General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are referenced

to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0 states by

writing to bit 3 through bit 0 of the IOPINS (R20) register.

3

4, 14

5

6

7

3, 4

VL

5, 6, 18, 19 GND

7

GPOUT2

8

GPOUT3

10

RES

Input

Input

Output

Input

Level-Translator Reference Voltage. Connect VL to the system’s 1.71V to 3.6V

logic-level power supply. Bypass VL to ground with a 0.1µF capacitor as close to

the VL pin as possible.

Ground

General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are referenced to

the voltage on VL. The SPI master controls the GPOUT3–GPOUT0 states by writing to

bit 3 through bit 0 of the IOPINS (R20) register.

Device Reset. Drive RES low to clear all of the internal registers except for

PINCTL (R17), USBCTL (R15), and SPI logic. See the Device Reset section for a

description of resets available on the MAX3420E.

SPI Serial-Clock Input. An external SPI master supplies this clock with frequencies

8

11

SCLK

Input up to 26MHz. The logic level is referenced to the voltage on VL. Data is clocked

into the SPI slave interface on the positive edge of SCLK. Data is clocked out of

the SPI slave interface on the falling edge of SCLK.

SPI Slave-Select Input. The SS logic level is referenced to the voltage on VL.

When SS is driven high, the SPI slave interface is not selected and SCLK

9

12

SS

Input

transitions are ignored. An SPI transfer begins with a high-to-low SS transition and

ends with a low-to-high SS transition. The MAX3420E SS pin is sensitive to

undershoot. A 33pF capacitor should be connected from SS to ground to prevent

any noise spikes.*

SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO is

10

13

MISO

Output tri-stated in half-duplex mode or when SS = 1. The MISO logic level is referenced

to the voltage on VL.

Input or SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is

11

14

MOSI

Input/ referenced to the voltage on VL. MOSI can also be configured as a bidirectional

Output MOSI/MISO input and output.

General-Purpose Multiplexed Output. The internal MAX3420E signal that appears

12

15

GPX

Output on GPX is programmable by writing to the GPXB and GPXA bits of the PINCTL

(R17) register. GPX indicates one of four signals: OPERATE (00, Default),

VBUS_DET (01), BUSACT (10), and SOF (11).

Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage

on VL. In edge mode , INT is a push-pull output with programmable polarity. In level

13

17

INT

Output mode, INT is open drain and active low. Set the IE bit in the CPUCTL (R16) register to

enable INT.

15

20

D-

Input/

Output

USB D- Signal. Connect D- to a USB “B” connector through a 33Ω (±1%) series resistor.

*33pF capacitor will not be required after redesign.

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