MAX3420EECJ(2005) 查看數據表（PDF） - Maxim Integrated

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MAX3420EECJ
(Rev.:2005)

USB Peripheral Controller with SPI Interface

Maxim Integrated 

USB Peripheral Controller

with SPI Interface

Pin Description (continued)

PIN

TQFN

TQFP

16

21

NAME

D+

17

22, 23

VCC

18

24

VBCOMP

19

26

XI

20

27

XO

21

29

GPIN0

22

30

GPIN1

23

31

GPIN2

24

32

GPIN3

—

9, 16, 25, 28 N.C.

EP

—

GND

INPUT/

OUTPUT

FUNCTION

Input/

Output

Input

Input

Input

Output

USB D+ Signal. Connect D+ to a USB “B” connector through a 33Ω (±1%)

series resistor. The 1.5kΩ D+ pullup resistor is internal to the device.

USB Transceiver Power-Supply Input. Connect VCC to a positive 3.3V power

supply. Bypass VCC to ground with a 1.0µF ceramic capacitor as close to the

VCC pin as possible.

VBUS Comparator Input. VBCOMP is internally connected to a voltage

comparator to allow the SPI master to detect (through an interrupt or checking

a register bit) the presence or loss of power on VBUS. Bypass VBCOMP to

ground with a 1.0µF ceramic capacitor.

Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz

(±0.25%) crystal and a capacitor to GND. XI can also be driven by an external

clock referenced to VCC.

Crystal Oscillator Output. Connect XO to the other side of a parallel resonant

12MHz (±0.25%) crystal and a capacitor to GND. Leave XO unconnected if XI

is driven with an external source.

Input

General-Purpose Inputs. GPIN3–GPIN0 are connected to VL with internal

pullup resistors. GPIN3–GPIN0 logic levels are referenced to the voltage on VL.

The SPI master samples GPIN3–GPIN0 states by reading bit 7 through bit 4 of

the IOPINS (R20) register. Writing to these bits has no effect.

—

Input

No Internal Connection

Exposed Paddle on the Bottom of the TQFN Package. Connect EP to GND.

Register Description

The SPI master controls the MAX3420E by reading and

writing 21 registers (Table 1). For a complete descrip-

tion of register contents, please refer to the “MAX3420E

Programming Guide.” A register access consists of the

SPI master first writing an SPI command byte, followed

by reading or writing the contents of the addressed

register. All SPI transfers are MSB (most significant bit)

first. The command byte contains the register address,

a direction bit (Read = 0, Write = 1), and the ACKSTAT

bit (Figure 4). The SPI master addresses the

MAX3420E registers by writing the binary value of the

register number in the Reg4 through Reg0 bits of the

command byte. For example, to access the IOPINS

(R20) register, the Reg4 through Reg0 bits would be as

follows: Reg4 = 1, Reg3 = 0, Reg2 = 1, Reg1 = 0, Reg0

= 0. The DIR (direction) bit determines the direction for

the data transfer. DIR = 1 means the data byte(s) will

be written to the register, and DIR = 0 means the data

byte(s) will be read from the register. The ACKSTAT bit

sets the ACKSTAT bit in the EPSTALLS (R9) register.

The SPI master sets this bit to indicate that it has fin-

ished servicing a CONTROL transfer. Since the bit is

frequently used, having it in the SPI command byte

improves firmware efficiency. In SPI full-duplex mode,

the MAX3420E clocks out eight USB status bits as the

command byte is clocked in (Figure 5). In half-duplex

b7

b6

b5

b4

b3

b2

Reg4

Reg3

Reg2

Reg1

Reg0

0

Figure 4. SPI Command Byte

b1

b0

DIR

ACKSTAT

b7

b6

b5

b4

b3

b2

b1

SUSPIRQ

URESIRQ

SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ

Figure 5. USB Status Bits Clocked Out as First Byte of Every Transfer (Full-Duplex Mode Only)

b0

IN0BAVIRQ

_______________________________________________________________________________________ 5

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