MAX3625 查看數據表（PDF） - Maxim Integrated
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MAX3625 Datasheet PDF : 10 Pages
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19-1010; Rev 0; 10/07
Low-Jitter, Precision Clock Generator
with Three Outputs
General Description
The MAX3625 is a low-jitter precision clock generator
optimized for networking applications. The device inte-
grates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet, 10G Fibre Channel, and other net-
working applications.
Maxim’s proprietary PLL design features ultra-low jitter
and excellent power-supply noise rejection, minimizing
design risk for network equipment.
The MAX3625 has three LVPECL outputs. Selectable
output dividers and a selectable feedback divider allow
a range of output frequencies.
Features
♦ Crystal Oscillator Interface: 24.8MHz to 27MHz
♦ CMOS Input: Up to 320MHz
♦ Output Frequencies
Ethernet: 125MHz, 156.25MHz, 312.5MHz
10G Fibre Channel: 159.375MHz, 318.75MHz
♦ Low Jitter
0.14psRMS (1.875MHz to 20MHz)
0.38psRMS (12kHz to 20MHz)
♦ Excellent Power-Supply Noise Rejection
♦ No External Loop Filter Capacitor Required
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
IN_SEL
MR
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX3625CUG+ 0°C to +70°C 24 TSSOP
+Denotes a lead-free package.
PKG
CODE
U24-1
BYPASS
SELA[1:0]
Block Diagram
REF_IN
27pF
X_IN
X_OUT
33pF
SELA[1:0]
SELB[1:0]
FB_SEL
BYPASS
RESET LOGIC/POR
RESET
LVCMOS
0
1
CRYSTAL
OSCILLATOR
DIVIDERS:
M = 24, 25
NA = 1, 2, 4, 5
NB = 1, 2, 4, 5
0
620MHz TO 648MHz
PFD
FILTER
VCO
1
RESET
DIVIDER
M
MAX3625
DIVIDER
NA
RESET
LVPECL
BUFFER
RESET
DIVIDER
NB
LVPECL
BUFFER
LVPECL
BUFFER
QA_OE
QA
QA
QB1
QB1
QB_OE
QB0
QB0
FB_SEL
SELB[1:0]
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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