MAX3679 查看數據表（PDF） - Maxim Integrated

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MAX3679

+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

Maxim Integrated 

+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

Table 1. Output Frequency Determination Chart

XO OR CMOS

INPUT

FREQUENCY

(MHz)

25

FEEDBACK

DIVIDER, M

25

VCO

FREQUENCY

(MHz)

625

OUTPUT

DIVIDER,

NA AND NB

÷2

÷4

÷5

÷10

OUTPUT

FREQUENCY

(MHz)

312.5

156.25

125

62.5

APPLICATIONS

Ethernet

Table 2. Output Divider Configuration Chart

INPUT

SELA1/SELB1

SELA0/SELB0

0

0

1

0

1

1

NA/NB DIVIDER

÷2*

÷4

÷5

0

OPEN

÷10

*Maximum guaranteed output frequency is 160MHz for CMOS

and 320MHz for LVPECL output.

Table 3. Crystal Selection Parameters

PARAMETER SYMBOL MIN

Crystal Oscillation

Frequency

fOSC

Shunt Capacitance CO

Load Capacitance

CL

Equivalent Series

Resistance (ESR)

RS

Maximum Crystal

TYP MAX UNITS

25

MHz

2.0 7.0 pF

18

pF

50

300 μW

27pF

25MHz CRYSTAL

(CL = 18pF)

33pF

X_IN

X_OUT

Figure 4. Crystal, Capacitors Connection

Figure 3. Crystal Layout

Crystal Selection

The crystal oscillator is designed to drive a fundamental

mode, AT-cut crystal resonator. See Table 3 for recom-

mended crystal specifications. See Figure 4 for external

capacitance connection.

Crystal Input Layout and

Frequency Stability

The crystal, trace, and two external capacitors should

be placed on the board as close as possible to the

MAX3679’s X_IN and X_OUT pins to reduce crosstalk

of active signals into the oscillator.

The layout shown in Figure 3 gives approximately 3pF

of trace plus footprint capacitors per side of the crystal

(Y1). The dielectric material is FR-4 and dielectric thick-

ness of the reference board is 15 mils. Using a 25MHz

crystal and the capacitor values of C22 = 27pF and

C23 = 33pF, the measured output frequency accuracy

is -14ppm at +25°C ambient temperature.

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