MAX3625A 查看數據表（PDF） - Maxim Integrated

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MAX3625A

Low-Jitter, Precision Clock Generator with Three Outputs

Maxim Integrated 

Low-Jitter, Precision Clock

Generator with Three Outputs

Layout Considerations

The inputs and outputs are critical paths for the

MAX3625A, and care should be taken to minimize dis-

continuities on these transmission lines. Here are some

suggestions for maximizing the MAX3625A’s perfor-

mance:

• An uninterrupted ground plane should be posi-

tioned beneath the clock I/Os.

• Supply and ground pin vias should be placed

close to the IC and the input/output interfaces to

allow a return current path to the MAX3625A and

the receive devices.

• Supply decoupling capacitors should be placed

close to the MAX3625A supply pins.

• Maintain 100Ω differential (or 50Ω single-ended)

transmission line impedance out of the MAX3625A.

• Use good high-frequency layout techniques and

multilayer boards with an uninterrupted ground

plane to minimize EMI and crosstalk.

Refer to the MAX3625A Evaluation Kit for more information.

Chip Information

TRANSISTOR COUNT: 10,840

PROCESS: BiCMOS

Pin Configuration

TOP VIEW

SELB0 1

BYPASS 2

MR 3

VCCO_A 4

QA 5

QA 6

QB_OE 7

QA_OE 8

FB_SEL 9

VCCA 10

VCC 11

SELA0 12

MAX3625A

24 SELB1

23 VCCO_B

22 QB0

21 QB0

20 QB1

19 QB1

18 IN_SEL

17 REF_IN

16 X_IN

15 X_OUT

14 GND

13 SELA1

TSSOP

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