MAX3625B 查看數據表（PDF） - Maxim Integrated

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MAX3625B

Low-Jitter, Precision Clock Generator with Three Outputs

Maxim Integrated 

Low-Jitter, Precision Clock

Generator with Three Outputs

PIN

10

11

12, 13

14

15

16

17

18

19

20

21

22

23

—

Pin Description (continued)

NAME

VCCA

VCC

SELA0,

SELA1

GND

X_OUT

X_IN

REF_IN

IN_SEL

QB1

QB1

QB0

QB0

VCCO_B

EP

FUNCTION

Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this

pin can connect to VCC through 10.5
as shown in Figure 1 (requires VCC = 3.3V ±5%).

Core Power Supply. Connect to +3.3V.

LVCMOS/LVTTL Inputs. Control NA divider setting. See Table 2 for more information. 50k
input

impedance.

Supply Ground

Crystal Oscillator Output

Crystal Oscillator Input

LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.

LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has

internal 75k
pullup to VCC.

LVPECL, Inverting Clock Output

LVPECL, Noninverting Clock Output

LVPECL, Inverting Clock Output

LVPECL, Noninverting Clock Output

Power Supply for QB0 and QB1 Clock Output. Connect to +3.3V.

Exposed Pad. Supply ground; connect to PCB ground for proper electrical and thermal performance.

Detailed Description

The MAX3625B is a low-jitter clock generator designed

to operate at Ethernet and Fibre Channel frequencies. It

consists of an on-chip crystal oscillator, PLL, program-

mable dividers, and LVPECL output buffers. Using a

low-frequency clock (crystal or CMOS input) as a refer-

ence, the internal PLL generates a high-frequency out-

put clock with excellent jitter performance.

Crystal Oscillator

An integrated oscillator provides the low-frequency ref-

erence clock for the PLL. This oscillator requires an

external crystal connected between X_IN and X_OUT.

The crystal frequency is 24.8MHz to 27MHz.

REF_IN Buffer

An LVCMOS-compatible clock source can be connect-

ed to REF_IN to serve as the reference clock.

The LVCMOS REF_IN buffer is internally biased to the

threshold voltage (1.4V typ) to allow AC- or DC-cou-

pling, and is designed to operate up to 320MHz.

PLL

The PLL takes the signal from the crystal oscillator or

reference clock input and synthesizes a low-jitter, high-

frequency clock. The PLL contains a phase-frequency

detector (PFD), a lowpass filter, and a voltage-

controlled oscillator (VCO) with a 620MHz to 648MHz

operating range. The VCO is connected to the PFD

input through a feedback divider. See Table 3 for

divider values. The PFD compares the reference fre-

quency to the divided-down VCO output (fVCO/M) and

generates a control signal that keeps the VCO locked

to the reference clock. The high-frequency VCO output

clock is sent to the output dividers. To minimize noise-

induced jitter, the VCO supply (VCCA) is isolated from

the core logic and output buffer supplies.

Output Dividers

The output dividers are programmable to allow a range of

output frequencies. See Table 2 for the divider input set-

tings. The output dividers are automatically set to divide by

1 when the MAX3625B is in bypass mode (BYPASS = 0).

VCC

10.5Ω

+3.3V ±5%

0.01μF

VCCA

0.01μF 10μF

Figure 1. Analog Supply Filtering

6 _______________________________________________________________________________________

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