MAX5200ACUB 查看數據表（PDF） - Maxim Integrated
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MAX5200ACUB Datasheet PDF : 13 Pages
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Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
ELECTRICAL CHARACTERISTICS—MAX5202/MAX5203 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10kΩ in parallel with 250pF, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
INTERNAL REFERENCE
VREF Output Voltage
TA = +25°C
VREF Tempco
TA = 0°C to +70°C
TA = -40°C to +105°C
DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VHYST
Input Leakage
Input Capacitance
IIN
Digital inputs = 0 or VDD
CIN
POWER REQUIREMENTS
Positive Power Supply
VDD
Positive Supply Current
Shutdown Supply Current
IDD
ISHDN
All digital inputs at 0 or VDD (Note 5)
All digital inputs at 0 or VDD
TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
SCLK Clock Period
tCP
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
DIN Setup Time
DIN Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
LDAC Pulse Width
CS Rise to LDAC Low Setup
SCLK Fall to CS Fall Ignore
CS Pulse Width Low for Shutdown
CS Pulse Width High
tDS
tDH
tCSS
tCSH
tCS0
tCS1
tLDAC
tLDACS
tCSOL
tCSWL
tCSWH
MIN TYP MAX UNITS
1.46
1.5
1.54
V
±15
ppm/°C
±20
2.1
V
0.6
V
200
mV
±1
µA
15
pF
2.7
3.6
V
0.8
1.5
mA
1
10
µA
10
MHz
100
ns
40
ns
40
ns
40
ns
0
ns
40
ns
0
ns
10
ns
40
ns
40
ns
40
ns
10
ns
40
ns
100
ns
Note 1: Static performance tested at VDD = +5.0V (MAX5200/MAX5201) and at VDD = +3.0V (MAX5202/MAX5203).
Note 2: INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V).
Note 3: Guaranteed monotonic.
Note 4: VREF = 2.5V (MAX5200/MAX5201) and VREF = 1.5V (MAX5202/MAX5203).
Note 5: RL = ∞, digital inputs are at VDD or DGND.
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