MAX5258 查看數據表（PDF） - Maxim Integrated
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MAX5258 Datasheet PDF : 20 Pages
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+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
TIMING CHARACTERISTICS (MAX5259)
(VREF = +2.5V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and
TA = +25°C.)
PARAMETER
VDD Rise-to-CS Fall-Setup Time
LDAC Pulse Width Low
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
CS Pulse Width High
SCLK Clock Frequency (Note 5)
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall-to-SCLK Rise-Setup Time
SCLK Rise-to-CS Rise-Hold Time
DIN to SCLK Rise-to-Setup Time
DIN to SCLK Rise-to-Hold Time
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
SYMBOL
tVDCS
tLDAC
tCLL
tCSW
fCLK
tCH
tCL
tCSS
tCSH
tDS
tDH
tDO1
CONDITIONS
MIN TYP MAX UNITS
5
µs
40
20
ns
40
ns
90
10
40
40
40
0
40
0
ns
MHz
ns
ns
ns
ns
ns
ns
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
tDO2
210
ns
CS Rise-to-SCLK Rise-Setup
Time
tCS1
40
ns
Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of VOUT.
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for tLDAC or longer after CS goes high.
Note 5: When DOUT is not used. If DOUT is used, fCLK (max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
6 _______________________________________________________________________________________
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