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MAX5408(2002) 查看數據表(PDF) - Maxim Integrated

零件编号
产品描述 (功能)
生产厂家
MAX5408
(Rev.:2002)
MaximIC
Maxim Integrated MaximIC
MAX5408 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Dual, Audio, Log Taper Digital Potentiometers
Table 1. Serial Interface Programming Commands for MAX5408/MAX5410
8-BIT SERIAL WORD
A0
A1
A2
D4–D0
0
0
0
5-bit DAC data
FUNCTION
Set position of wiper W0A
0
0
0
1
0
1
1
0
1
5-bit DAC data
No change
0
5-bit DAC data
Set position of wiper W1A
1
5-bit DAC data
No change
0
4-bit mute data, D0 = dont care
Data for mute register (see Table 3)
1
0
1
4-bit zero-crossing detection data,
D0 = dont care
Data for zero-crossing detection register
(see Table 5)
1
1
0
00000
Readback contents of wiper register for W0A
at DOUT
1
1
0
00001
No change
1
1
0
00010
Readback contents of wiper register for W1A
at DOUT
1
1
1
1
0
00011
0
00100
No change
Readback contents of mute register at DOUT
1
1
1
1
0
00101
1
D4 = 0, D3D0 = dont care
Readback contents of zero-crossing detection
register at DOUT
Immediate update then analog power-down
when zero crossing is enabled. No effect
when zero crossing is disabled.
Detailed Description
Digital Serial Interface
An SPI-compatible serial interface controls the
MAX5408MAX5411. The input word to the device is
eight bits long, composed of three address bits (A0,
A1, and A2), followed by five data bits, with MSB first
(see Tables 1 and 2). The first three address bits set
the value of internal registers. The five data bits control
the wiper position. For certain commands, some of the
five data bits are dont cares, but must be sent to the
device.
The serial data is listed in Tables 1 and 2.
The control code determines:
Potentiometer to update or register to set.
Data for mute register (Tables 3 and 4).
Data for zero-crossing detection register (Tables 5
and 6).
The data bits control the position of the wiper (Table 7).
A logic low on the chip-select input (CS) enables the
devices serial interface. A logic high on CS disables
the interface control circuitry. See Figure 1 for serial-
interface timing description.
CS
SCLK
DIN
DOUT
tCSS
tCH
tCL
tDS
tDH
CS
SCLK
tCSW
tCP
tCSH
tCSI
DIN
tDO
DOUT
tIW
WIPER
Figure 1. Serial Timing Diagram
6 _______________________________________________________________________________________

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