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MAX6423US17-T

Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay

Maxim Integrated 

Low-Power, SC70/SOT µP Reset Circuits with

Capacitor-Adjustable Reset Timeout Delay

Pin Description

MAX6340

SOT23

PIN

MAX6421

MAX6422

MAX6423

SOT143 SC70

MAX6424

MAX6425

MAX6426

NAME

SOT23 SOT23

FUNCTION

Set Reset Timeout Input. Connect a capacitor between SRT

1

3

3

5

1

SRT

and ground to set the timeout period. Determine the period as

follows: tRP = 2.73 ✕ 106 ✕ CSRT + 275µs with tRP in seconds

and CSRT in farads.

2

1

2

3

2, 3

GND Ground

3

—

—

4

—

N.C. Not Internally Connected. Can be connected to GND.

4

2

1

2

5

VCC Supply Voltage and Reset Threshold Monitor Input

RESET changes from high to low whenever VCC drops below

5

1

4

RESET the selected reset threshold voltage. RESET remains low for

the reset timeout period after VCC exceeds the reset

threshold.

4

4

RESET changes from low to high whenever VCC drops below

—

—

—

RESET

the selected reset threshold voltage. RESET remains high for

the reset timeout period after VCC exceeds the reset

threshold.

Detailed Description

Reset Output

The reset output is typically connected to the reset input

of a µP. A µP’s reset input starts or restarts the µP in a

known state. The MAX6340/MAX6421–MAX6426 µP

supervisory circuits provide the reset logic to prevent

code-execution errors during power-up, power-down,

and brownout conditions (see Typical Operating

Characteristics).

RESET changes from high to low whenever VCC drops

below the threshold voltage. Once VCC exceeds the

threshold voltage, RESET remains low for the capacitor-

adjustable reset timeout period.

The MAX6422 active-high RESET output is the inverse

logic of the active-low RESET output. All device outputs

are guaranteed valid for VCC > 1V.

The MAX6340/MAX6423/MAX6425/MAX6426 are open-

drain RESET outputs. Connect an external pullup resis-

tor to any supply from 0 to 5.5V. Select a resistor value

large enough to register a logic low when RESET is

asserted and small enough to register a logic high

while supplying all input current and leakage paths

connected to the RESET line. A 10kΩ to 100kΩ pullup

is sufficient in most applications.

3.3V

VCC

5.0V

LASER-TRIMMED

RESISTORS

VREF

SRT RESET

TIMEOUT

CSRT

MAX6340

MAX6423

MAX6425

MAX6426

RESET

N

10kΩ

5V

SYSTEM

GND

Figure 1. MAX6340/MAX6423/MAX6425/MAX6426 Open-Drain

RESET Output Allows Use with Multiple Supplies

Selecting a Reset Capacitor

The reset timeout period is adjustable to accommodate

a variety of µP applications. Adjust the reset timeout

period (tRP) by connecting a capacitor (CSRT) between

SRT and ground. Calculate the reset timeout capacitor

as follows:

4 _______________________________________________________________________________________

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