MAX7409 查看數據表（PDF） - Maxim Integrated

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MAX7409

5th-Order, Lowpass, Switched-Capacitor Filters

Maxim Integrated 

5th-Order, Lowpass,

Switched-Capacitor Filters

Low-Power Shutdown Mode

These devices feature a shutdown mode that is activat-

ed by driving SHDN low. In shutdown mode, the filter’s

supply current reduces to 0.2µA and its output becomes

high impedance. For normal operation, drive SHDN

high or connect it to VDD.

__________Applications Information

Offset and Common-Mode

Input Adjustment

The COM pin sets the common-mode input voltage and

is biased at mid-supply with an internal resistor-divider.

If the application does not require offset adjustment,

connect OS to COM. For applications requiring offset

adjustment, apply an external bias voltage through a

resistor-divider network to OS such as shown in Fig-

ure 3. For applications that require DC level shifting,

adjust OS with respect to COM. (Note: OS should not

be left unconnected.) The output voltage is represent-

ed by this equation:

VOUT = (VIN - VCOM) + VOS

with VCOM = VDD / 2 (typical), and where (VIN - VCOM)

is lowpass filtered by the SCF, and OS is added at the

output stage. See the Electrical Characteristics for the

voltage range of COM and OS. Changing the voltage

on COM or OS significantly from midsupply reduces

the filter’s dynamic range.

Power Supplies

The MAX7409/MAX7410 operate from a single +5V

supply and the MAX7413/MAX7414 operate from a sin-

gle +3V supply. Bypass VDD to GND with a 0.1µF

capacitor. If dual supplies are required (±2.5V for

MAX7409/MAX7410, ±1.5V for MAX7413/MAX7414),

connect COM to system ground and connect GND to

the negative supply. Figure 4 shows an example of

dual-supply operation. Single- and dual-supply perfor-

mance are equivalent. For either single- or dual-supply

operation, drive CLK and SHDN from GND (V- in dual-

supply operation) to VDD. For ±5V dual-supply applica-

tions, use the MAX291–MAX297.

Input Signal Amplitude Range

The optimal input signal range is determined by

observing the voltage level at which the Total Harmonic

Distortion + Noise is minimized for a given corner fre-

quency. The Typical Operating Characteristics show

graphs of the devices’ Total Harmonic Distortion plus

Noise Response as the input signal’s peak-to-peak

amplitude is varied.

VSUPPLY

0.1µF

INPUT

CLOCK

VDD

SHDN

OUT

OUTPUT

IN

COM

0.1µF

50k

MAX7409

MAX7410

CLK

MAX7413

MAX7414

OS

50k

0.1µF

50k

GND

Figure 3. Offset Adjustment Circuit

V+

INPUT IN

VDD

SHDN *

OUT OUTPUT

COM

MAX7409

V+

V-

CLOCK

CLK

MAX7410

MAX7413

OS

MAX7414

0.1µF

0.1µF

GND

V-

*DRIVE SHDN TO V- FOR LOW-POWER SHUTDOWN MODE.

Figure 4. Dual-Supply Operation

Anti-Aliasing and DAC Postfiltering

When using these devices for anti-aliasing or DAC

postfiltering, synchronize the DAC (or ADC) and the fil-

ter clocks. If the clocks are not synchronized, beat fre-

quencies will alias into the desired passband.

Harmonic Distortion

Harmonic distortion arises from nonlinearities within the

filter. These nonlinearities generate harmonics when a

pure sine wave is applied to the filter input. Table 1 lists

typical harmonic-distortion values for the MAX7410/

MAX7414 with a 10kΩ load at TA = +25°C. Table 2 lists

typical harmonic-distortion values for the MAX7409/

MAX7413 with a 10kΩ load at TA = +25°C.

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