MAX817LCPA 查看數據表（PDF） - Maxim Integrated

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MAX817LCPA

+5V Microprocessor Supervisory Circuits

Maxim Integrated 

+5V Microprocessor Supervisory Circuits

desired trip point (VTRIP). Resistor R3 adds hysteresis.

It will typically be an order of magnitude greater than R1

or R2. The current through R1 and R2 should be at least

1µA to ensure that the 25nA (max) PFI input leakage

current does not shift the trip point. R3 should be larger

than 200kΩ to prevent it from loading down the PFO pin.

Capacitor C1 adds additional noise rejection.

Monitoring an Additional Supply

(MAX817/MAX819)

The MAX817/MAX819 µP supervisors can monitor either

positive or negative supplies using a resistor voltage

divider to PFI. PFO can be used to generate an interrupt

to the µP or to trigger a reset (Figures 9 and 13).

Interfacing to µPs with

Bidirectional Reset Pins

µPs with bidirectional reset pins, such as the Motorola

68HC11 series, can contend with the MAX817/MAX818/

MAX819 RESET output. If, for example, the RESET out-

put is driven high and the µP wants to pull it low, inde-

terminate logic levels may result. To correct this,

connect a 4.7kΩ resistor between the RESET output

and the µP reset I/O, as in Figure 14. Buffer the RESET

output to other system components.

Negative-Going VCC Transients

These supervisors are relatively immune to short-dura-

tion, negative-going VCC transients (glitches) while

issuing a reset to the µP during power-up, power-down,

and brownout conditions. Therefore, resetting the µP

when VCC experiences only small glitches is usually not

desirable.

The Typical Operating Characteristics show a graph of

Maximum Transient Duration vs. Reset Threshold

Overdrive for which reset pulses are not generated. The

graph was produced using negative-going VCC pulses,

starting at 3.3V and ending below the reset threshold by

the magnitude indicated (reset threshold overdrive). The

graph shows the maximum pulse width that a negative-

going VCC transient can typically have without triggering

a reset pulse. As the amplitude of the transient increases

(i.e., goes farther below the reset threshold), the maxi-

mum allowable pulse width decreases. Typically, a VCC

transient that goes 100mV below the reset threshold and

lasts for 135µs will not trigger a reset pulse.

A 0.1µF bypass capacitor mounted close to the VCC

pin provides additional transient immunity.

+5V

R1

R2

VCC

PFI

MAX817

MAX819

PFO

GND

V-

+5V

PFO

0V

VTRIP

0V

V-

5 - 1.25 = 1.25 - VTRIP

R1

R2

NOTE: VTRIP IS NEGATIVE

Figure 13. Monitoring a Negative Voltage

BUFFERED RESET TO OTHER SYSTEM COMPONENTS

VCC

MAX817

MAX818

MAX819

4.7k

RESET

GND

VCC

RESET

GND

Figure 14. Interfacing to µPs with Bidirectional Reset I/O

14 ______________________________________________________________________________________

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