MAX817LCPA 查看數據表（PDF） - Maxim Integrated

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MAX817LCPA

+5V Microprocessor Supervisory Circuits

Maxim Integrated 

+5V Microprocessor Supervisory Circuits

Watchdog Software Considerations

(MAX817/MAX818)

To help the watchdog timer monitor software execution

more closely, set and reset the watchdog input at different

points in the program, rather than “pulsing” the watchdog

input high-low-high or low-high-low. This technique avoids

a “stuck” loop, in which the watchdog timer would contin-

ue to be reset within the loop, keeping the watchdog from

timing out. Figure 15 shows an example of a flow diagram

where the I/O driving the watchdog input is set high at the

beginning of the program, set low at the beginning of

every subroutine or loop, then set high again when the

program returns to the beginning. If the program should

“hang” in any subroutine, the problem would quickly be

corrected, since the I/O is continually set low and the

watchdog timer is allowed to time out, triggering a reset or

an interrupt. As described in the Watchdog Input Current

section, this scheme results in higher average WDI input

current than does the method of leaving WDI low for the

majority of the timeout period and periodically pulsing it

low-high-low.

START

SET

WDI

LOW

SUBROUTINE

OR PROGRAM LOOP,

SET WDI

HIGH

RETURN

END

Figure 15. Watchdog Flow Diagram

__________Typical Operating Circuit ____Pin Configurations (continued)

TOP VIEW

+5V

0.1µF

VCC

BATT

OUT

0.1µF

MAX817

MAX818

MAX819

RESET

CMOS

RAM

0.1µF

WDI**

CE IN* CE OUT*

GND

REAL-

TIME

CLOCK

ADDRESS

DECODE

A0–A15

RESET

µP

I/O

*CE IN AND CE OUT APPLY TO MAX818 ONLY.

**WDI APPLIES TO MAX817/MAX818 ONLY.

OUT 1

VCC 2

GND 3

CE IN 4

MAX818

8 BATT

7 RESET

6 WDI

5 CE OUT

DIP/SO/µMAX

OUT 1

VCC 2

GND 3

PFI 4

MAX819

8 BATT

7 RESET

6 MR

5 PFO

DIP/SO/µMAX

______________________________________________________________________________________ 15

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